By Mike Fitton, Senior Director of Strategic Planning and Business Development, Achronix (www.achronix.com)
We are currently in a transformational time for cellular connectivity, and the future of ubiquitous wireless is emerging. Worldwide successes in 2G, 3G and 4G have driven cell phone use to an incredible 7.5 billion mobile devices  . Astoundingly, this makes mobile devices more numerous as the world’s population. Perhaps more impactful is the effect that cellular connectivity is having on those who were previously digitally disenfranchised; for example, in 2016 sub-Saharan Africa had approximately one landline per 100 people, but 74 mobile connections.
As we look to the next decade, wireless infrastructure will become even more pervasive and even more integrated with every aspect of our everyday lives with the advent of 5G. 5G continues the paradigm of previous cellular standards (in driving bandwidth) but also extends it to many more devices and usage models.
Key trends include:
Increased bandwidth for Enhanced Mobile Broadband (eMBB) and other applications specifically driving the instantaneous available bandwidth to 10x current throughput or more.
- This will be the first drive with 5G standardization with 3GPP already complete for Non-Standalone (i.e. LTE assist) New Radio (NR) in 2017, with Standalone 5G available in 2018 as shown in Figure 1.
- Deployment of 5G will also be staged depending on frequency band, with sub-6GHz being deployed first, followed by the contiguous bands at mmWave frequencies enabling key eMBB applications at a later stage.
Figure 1: Timelines for 5G from the International Telecommunication Union (ITU) and 3rd Generation Partnership Project (3GPP).
Connectivity to many, many more devices with the advent of cellular connectivity for the Internet of Things (IoT). Expectations are that there will be 50-billion cellular connected devices by 2020 [ref]. This is somewhat addressed by existing standards but will also be encompassed by the current specification of Massive Machine Type Communications (mMTC) in Release 16.
Proliferation of new usage models exerting new requirements onto mobile devices and the cellular infrastructure that they connect to. Examples include:
- Low bandwidth, low-power requirements for connecting multiple battery-powered IoT end-points for connectivity and monitoring encompassed within mMTC;
- High-reliability, low-latency cellular for vehicle-to-vehicle and vehicle-to-infrastructure connectivity (C-V2X) to complement existing V2X solutions
- High-reliability, low-latency support for new and emerging applications like remote surgery and augmented/virtual-reality
The second two applications will be addressed by the upcoming 3GPP standard for Ultra-Reliable, Low-Latency Connectivity (URLLC).
Emerging need for Edge Analytics and Mobile Edge Compute. Gravity has shifted from the previous assumption of data moving to centralized compute resource for processing to a new paradigm of the compute resource moving toward where the data is generated. The reasons for this are manifold: strict latency requirements of emerging applications, sheer volume of data and the desire to optimize scarce networking resource, to name but a few.
This article considers how the unique requirements of 5G can be addressed by a system-on-chip (SoC architecture) with a high performance CPU subsystem and hardware processing elements, including field programmable gate array (FPGA) re-programmable acceleration.
The baseband takes the data from the network interface (e.g. Ethernet) and transforms it to/from complex samples that are transmitted over the front haul interface to the Radio. The high-level block diagram is included in 2a for LTE downlink transmitter and 2b for uplink receiver.
Figures 2a and 2b: An example of a high-level block diagram of baseband processing.
Case study of Baseband L1 processing
Let’s examine how the Baseband processing (specifically Layer-1) can be mapped onto key processing elements such as the processor subsystem, CPU and DSP cores, and fixed and flexible hardware acceleration as shown in Figure 3.
Figure 3 caption: Key baseband processing elements can be mapped onto key processing elements.
Front haul (Antenna Interface) Connectivity
In addition to the processing elements previously described, there is a flexible antenna interface block; this is the element is required to connect from the Baseband to the Radio Unit. Traditionally, this was Common Public Radio Interface (CPRI), or sometimes Open Base Station Architecture Initiative (OBSAI).
Increasingly, there is a move to specify a more flexible fronthaul interface to allow a different mapping between Baseband and Radio (as shown in Figure 4). The IEEE has an ongoing activity on Next Generation Fronthaul Interface NGFI (IEEE1914), comprising of the IEEE1914.1 Standard for Packet-based Fronthaul Transport Networks and IEEE1914.3 Radio over Ethernet (RoE) Encapsulations and Mappings . In parallel, there are other industry initiatives that specify a 5G fronthaul interface and share similar aspects, for example eCPRI.
Due to the variety of different specifications, standards and requirements for the fronthaul interface, FPGAs are typically used to support this interface, as shown in Figure 3.
Discrete architecture for 5G time-to-market solution
Figure 4 maps the required processing elements for 5G onto a discrete implementation with separate devices for CPU SoCs, look-aside FPGA acceleration and antenna interfacing. This configuration reflects implementation that could deploy in 5G prototyping and early-production, before optimized 5G ASICs are available.
- CPU system-on-chip includes, for example, an Arm processing complex as well as DSP cores for Layer-1 processing and hardened accelerators, for fixed, well-defined functionality.
- In this example, it is assumed that an existing 4G ASIC SoC is available and therefore has general purpose acceleration (e.g. MACSEC) as well as LTE specific acceleration: Forward Error Correction (specifically turbo codec), Fast Fourier Transform, and Discrete Fourier Transform to support SC-FDMA on the uplink
- Flexible Antenna Interface
- As described earlier, the fronthaul antenna interface is well suited to an FPGA implementation. This is configured in-line, with the data flowing from the Radio Unit (on the uplink) and then the protocol being converted to something with standard connectivity like Ethernet
- Hardware Acceleration FPGA
- A look-aside acceleration FPGA implements all necessary computationally intensive functions unavailable on the base SoC. This can be 5G specific functions or those not yet envisioned.
- In the example shown here, a CCIX interconnect is used. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs and custom ASICs.
Figure 4: Here’s a look at a discrete architecture for 5G time-to-market solution.
Chiplet based 5G implementation
Figure 5 shows a comparable architecture as that shown in Figure 4 but reconfigured with a chiplet based approach. In this case, a higher bandwidth, lower latency and lower power interface is used to connect the CPU SoC die with a look-aside hardware acceleration chiplet. The FPGA device supporting the fronthaul connection to the Radio Unit is not package integrated in this example but could be; indeed it could be the same device chiplet as the hardware acceleration chiplet, if there are sufficient resources.
Figure 5: A chiplet-based approach offers greater integration.
The two primary techniques for package integration are with a silicon interposer or with an organic substrate and some form of Ultra-Short Reach (USR) transceiver.
Fully-integrated 5G implementation
Finally, Figure 6 shows the final, most integrated architecture for baseband considered here. This approach includes the same processing elements as previously with the same functionality, but with embedded FPGA monolithically integrated on the die.
Figure 6: A heterogeneous multicore SoC with monolithic integration applied to 5G Baseband.
This tightly integrated approach of monolithic integration has a number of benefits. This interface has even higher bandwidth, lower latency and lower energy-per-bit than that observed in a chiplet-based approach. Moreover, the resource mix can be tailored to the specific application under consideration and therefore unwanted interfaces, memory and core logic is avoided. This also results in the lowest unit cost of the three architectures under consideration.
As described previously, the primary objective here is to afford improved time-to-market, flexibility and future proofing. Time-to-market comes from the fact that the SoC can be taped-out earlier, as late changing modifications (e.g. the emergence of Polar Codes in 5G) can be targeted into embedded FPGA (eFPGA) rather than ASIC. Flexibility results from new or unexpected algorithms (e.g. new encryption standards) can be addressed in embedded programmable logic rather than software or external FPGA.
Finally, future proofing enables the SoC lifecycle to be extended, as the large emerging requirements, for example for new standards such as URLLC and mMTC, can be addressed by the existing product rather than requiring a new development.
The tight coupling of CPU and programmable acceleration (embedded or stand-alone FPGA) allows the developer to create a platform product that can be taken to multiple, different markets. This increases the market applicability of a specific product and improves the development return-on-investment. It can even include targeting (or re-targeting) of markets post-silicon; i.e. the inherent flexibility afforded by maximizing programmability allows considerable scope for innovation.
Perhaps more important from a 5G perspective, a highly programmable solution enables a faster time to market. For example, it is no longer necessary to delay an SoC tape out until standards are finalized; late changing requirements can be absorbed in software or programmable hardware. This is a powerful advantage with the relentless (and increasing) pressure for early 5G deployments, coupled with the continuing emergence of new standards.
About Mike Fitton
Mike Fitton received his Ph.D. from the University of Bristol, U.K. in the domain of wireless communications, spread spectrum and software defined radio. He has wide expertise in planning, strategy and wireless systems research and development.
Dr. Fitton has broad experience over 25 years in the wireless telecommunications domain, including product line management, system architecture, algorithm development and semiconductors across wireless operators, terminal development and most recently in communications infrastructure.He is currently the Senior Director of Strategic Planning and Business Development at Achronix, a privately held, fabless semiconductor corporation based in Santa Clara, Calif. with high-performance FPGA and embedded FPGA (eFPGA) IP solutions. Achronix’s broad portfolio of solutions supports innovation and accelerates feature velocity across multiple applications, including Machine Learning, Data Center and Communications Infrastructure.