Paper Submitted by Lauro Rizzatti, Verification Expert, Rizzatti
Hardware emulation is a strategically essential ingredient of a verification flow used in a broad range of applications. It’s also an expensive line item in a yearly budget because of a variety of factors including acquisition cost and expenses to keep it operational, usable, safe and in good working condition.
As chip design engineering and verification groups present their budgets for 2020, it’s useful to review the benefits of hardware emulation, and the range of parameters and engineering criteria that contribute to its cost of ownership (COO) before approving the purchase.
Thirty years ago, it was unusual for an engineering group to have a line item in their yearly budget for hardware emulation. That’s because emulators were hard to use, time consuming to deploy, cumbersome for design debugging, and costly to purchase, install and maintain. They were limited to testing a single design at a time with only one use model called in-circuit-emulation (ICE) and no remote access. Emulation had a questionable reputation and expensive COO, and used for only the largest, most complex designs.
Since then, enhancements have been made to hardware emulators for use in a broad range of applications, from hardware verification to early embedded software validation, at the intellectual property (IP) all the way up to system levels.
While hardware emulation’s COO is much more favorable today, the purchase decision continues to require evaluation and assessment of cost/benefits. Considerations include price and additional expenses for an emulator’s lifetime of three to five years to keep it operational, usable, safe and in good condition.
The COO normally amounts to a multiple of the purchase price because of cumulative expenses. Frequently, the COO decreases with each new generation due to manufacturing improvements. In a highly competitive environment like the hardware emulation sector, equipment suppliers regularly announce better, more powerful machines.
Three well-known electronic design automation (EDA) vendors –– Mentor, a Siemens Business, Cadence Design Systems and Synopsys –– provide hardware emulation platforms, all with unique technologies and architectures that make a COO comparison difficult. See Table 1.
None of the vendors publicly disclose pricing. One long-ago measurement compared emulator pricing by calculating its purchase price normalized on a “dollar-per-gate” basis. As a reference, in the early 1990s, the leading emulator was the System Realizer from Quickturn Design (now Cadence). It sold at about $3 per gate. Almost 30 years later, the price is below one “penny per gate.”
- Installation cost and infrastructure expenses to accommodate the hardware emulator on premises
- Operational expenses to use and operate
- Maintenance and recurring costs, including expenses for renting or amortizing the facility to keep the machine running and to ensure proper environmental conditions of temperature, humidity and pollution-free air
- Learning and training expenses to bring users/engineers up to speed on the use of the emulator
All told, a hardware emulator’s COO could exceed the purchase price by three to five times over four years.
Hardware emulators are implemented in large, heavy cabinets designed to accommodate numerous programmable devices necessary to map a wide range of design sizes. The weighty cabinets use up considerable space and stress the floor. They also consume electricity and generate heat.
All offerings are scalable and expandable to accommodate multi-billion application specific integrated circuit (ASIC)-equivalent gate designs. At the time of this writing, processor companies claim their top capacity needs reach close to 10-billion gates. The largest single box emulator provides a design capacity of two-and-half billion gates. Greater capacity is accommodated by interconnecting multiple cabinets.
While there are differences in dimensions and weights among the three platforms, all possess a large footprint that leads to significant installation costs. The commercial field programmable gate array (FPGA)-based emulator may have an edge since off-the-shelf FPGAs have larger capacities than the other approaches.
The differentiator among the three emulators is power consumption. Processor-based emulators are the most power hungry since processor devices are active all the time. While each has fans, the processor-based emulator demands additional cooling through fluid circulation that requires a piping system constraining placement. For security reasons regulated by strict OSHA laws, pipes cannot be too close to information technology (IT) equipment, further restricting locations for liquid-cooled machines. They are relegated to a corner of a building. Fans generate noise that require acoustic isolation as well.
Characteristics and constraints add up to increase installation cost, a one-time expense that ranges widely. The high end of the cost is reached when a premise must be built to accommodate a hardware emulator. The low-end is when an existing facility is setup to accommodate it.
Improvements to the technology eased most limitations of early emulators. Design compilation and design debug, two critical deployment areas, previously required a skilled and experienced staff to deploy and operate them. To a certain extent, that requirement still exists.
Talent and experience are scarce in the semiconductor industry, leading to high-compensation plans. In the U.S. technology area, compensation for such jobs may cost an employer $250,000 to $300,000 per year or so. Expenses for a staff of three experts could reach $1 million per year.
The commercial-based FPGA emulator’s technology is at a disadvantage because mapping a design on an array of off-the-shelf FPGAs needs some manual assistance from experienced engineers. Additionally, limited FPGA internal visibility slows down the design debugging process.
Maintenance and Recurring Costs
The cost for renting or amortizing the premises can vary and depends on the facility’s location.
Maintenance costs to keep an emulator running cover recurrent maintenance and repair expenses. The expense to ensure proper environmental conditions is the monthly electricity bill, different from emulator to emulator. The most power-thrifty emulator is close to 10 Watts-per-million gates (W/MG). An additional expense is required for running A/C, lighting and a variety of electronics and computers.
At the 10 W/MG rate, the emulator that consumes the least power with a one-billion gate capacity would consume 87,600-kilowatt hour (kWh) in one year (10 kW x 8,760 hours). It could double with additional expenses.
A processor-based emulator consumes more wattage, as much as an order of magnitude more than custom emulator on chip (EOC)- and commercial FPGA-based machines. Cleaning and replacing cooling fluids must be done on a regular basis, a similar task to changing the oil in a car.
Depending on the energy cost and the energy provider’s rate in the area, the energy bill for a one-billion gate emulator could be as high as several hundred thousand dollars per year.
Repair expenses happen during a failure. High values for Mean-Time-Between-Failures (MTBF) and low values for Mean-Time-To-Repair (MTTR) are essential for keeping these expenses to a minimum. In general, MTBF should be measured in several months or even a few years. Whenever a failure occurs, MTTR should be as short as possible. Optimally, less than a day.
Learning and Training Expenses
Despite the progress made in the technology, emulators are not push-button machines. While they are easier to deploy, operate and maintain than when first introduced, staffing resources to complete all tasks can affect the overall COO.
Training an engineer in emulation deployment is expensive and time consuming. It could take a minimum of three to six months of learning and an additional six months to a year to develop on-the-job experience. Based on considerations for the operational costs, the same level of expenses applies to train an engineer.
Training an engineer on a commercial-based FPGA emulator could take twice as long or longer than the other two technologies.
Gauging the success of emulation in the verification flow is its ability to find design bugs that no other verification technology can.
Unearthed bugs in the design-under-test (DUT) hardware after tape-out leads to re-spins. According to recent data, a re-spin at 7nm could be close to $30 million. Uncovered hardware and software bugs delay the time to market of a new chip. Several studies found that missing a schedule in a highly competitive market by three months shrinks product revenues by about 30%. For example, figure 1 represents a simplified model (Ateq model) to compute the revenue loss due to late market entry. The model assumes that revenue increases linearly until reaching a peak, and then decreases linearly to zero.
For a number of years, emulation benefits from an essential capability to accelerate bug finding. Known as virtual environment deployment it replaced physical peripherals in an ICE setup with equivalent software models. Virtual peripherals described at a high level of abstraction in C/C++ or SystemVerilog are processed in a host server connected to the emulator.
The shift to virtual emulation offered numerous advantages.
First, it opened the door to new use models beyond ICE and new verification tasks beyond hardware functional verification. A DUT based on a transactional interface mapped inside an emulator could be exercised by a software testbench executed in the host server. The software testbench could be a universal verification methodology (UVM) testbench, ideal for block-level verification, a peripheral or a set of peripherals or a software-stack executed by a fast model of an embedded CPU.
Second, the virtual approach combined with hardware/software advances for fast retrieval of DUT data made new tasks possible. Those include database generation for power analysis in the context of software processing, design-for-testability (DFT) analysis, deterministic ICE and new Apps, each targeting a specific verification challenge. Apps expand the emulation user community beyond the traditional deployment for acceleration. More verification tasks serving more users increase an emulator’s use and lower its COO.
Also, a virtual target system can be accessed remotely 24/7 worldwide. Manual assistance is not needed when a user swaps one design for another or a new user signs in. Today, emulators support multiple concurrent users, trading off total capacity for number of simultaneous users. This capability requires an efficient queuing and scheduling mechanism to manage multiple emulation jobs submitted simultaneously through a queuing process that prioritizes jobs for maximum utilization.
Likewise, system reliability improves with the absence of physical dependencies in a virtual environment, confirming that the virtual mode has a positive impact on the COO. More use modes and verification tasks, remote access and multiple concurrent users drop the COO by at least an order of magnitude from ICE mode.
Specifically, high throughput in virtual mode is essential for an improved COO, a benefit of the EOC-based emulation architecture. The emulation vendor that boasts the highest throughput offers an extended emulation Apps library that boosts the COO.
Additionally, the more concurrent users, the lower the COO. In this application, the processor-based emulator leads the pack. When deployed in a data center, a hardware emulator that is easier to use, provides faster design bring up and simplified debug needs fewer, less experienced engineers to operate is an easily justified purchase with a reduced COO.
Hardware emulation is a mandatory verification engine for the verification engineering community. While still the most expensive line item on the engineering manager’s budget, the purchasing manager should focus on its COO, keeping in mind that it can run three to five times its purchasing price over its lifetime. After a thorough and comprehensive analysis of the cost/benefits of emulation, implementing such a tool may help save millions of dollars.
About Lauro Rizzatti
Dr. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Previously, Dr. Rizzatti held positions in management, product marketing, technical marketing and engineering.