Electrostatic Discharge (ESD) precautions are well understood and implemented throughout all stages of semiconductor development (fabrication, assembly, test, device usage, and field failure analysis). Advanced packaging techniques such as 2.5D/3D exacerbate this problem, requiring special consideration. GSA, in association with the ESD Association and academia, investigated how this phenomenon differs in the 3D packaging environment. This extensive research, including case studies, is delineated in the GSA-ESDA 3D-IC ESD white paper.
Completed by the process design kit (PDK) developer and delivered with each new release of an mixed-signal PDK, this document provides a better understanding of the source data, completeness and quality of the PDK before it is used to design ICs or modified to fit into in-house design flow. The Checklist Users Guide has been combined with the checklist, in Version 4.0 (July 2013)
Supply Chain Merger & Acquisition and Integration Due Diligence
The Supply Chain Merger & Acquisition and Integration Due Diligence Checklist defines a broad spectrum of items to be addressed by supply chain management of both companies in a merger or acquisition. Targeted toward the Supply Chain Professional, this initial release remains in its early stages. Future work will extend the checklist to include Legal, Financial, Human Resources, and IT aspects.
The Quality Monitors Checklist provides the quality framework for semiconductor testing before product is shipped. It defines tests and parameters required to minimize the level of bad product shipped to an end customer.
While this is not meant to be a comprehensive list, the Quality Monitors Checklist can be used to:
Analyze gaps in testing
Provide the top 3-5 test areas for each line of defense against shipping low-quality product
Improve customer awareness by providing a guideline for customers to better understand the test environment
GSA’s AMS/RF PCM/Process Checklist Sub-Working developed a checklist that provides (1) a recommended list of parameters that foundries should measure (i.e., test), (2) a uniform way to measure each parameter (i.e., describe the measurement) and (3) a consistent way to describe the test data.
The checklist includes:
Device (e.g., FET)
Parameter (e.g., Drain-Source Breakdown)
Parameter Measurement Definition
Parameter Class (e.g., Reliability)
Units (e.g., Volts)
Type (e.g., N/P)
Category (e.g., Pass/Fail)
Fabless and fab-lite companies, which are the targeted users of the Checklist, benefit from using the tool as it helps them better understand and use the parameter data they receive from their foundry partners. Better understanding yield and how it is affected by various PCM parameters allows fabless companies to design higher yielding chips.
The AMS/RF Process Checklist reflects the key attributes of an AMS/RF foundry process offering. It provides standard definitions for quantitative and qualitative metrics, which can be used for classification, as well as figures of merit in selecting an appropriate process and process options for a specific design application. Three important needs have been identified for the AMS/RF Process Checklist: It identifies the different elements of a foundry’s AMS/RF process and its ability to fulfill a semiconductor company’s needs; it serves as a basic set of guidelines for measuring available items in an AMS/RF foundry process; and, it is an efficient way to communicate information in a consistent format across all foundries.
The checklist includes the seven key attributes of an AMS/RF foundry process offering:
The GSA Mixed-Signal/RF SPICE Model Checklist is a document completed by a SPICE modeling engineer/department and delivered with each release of a SPICE model set. The first part of this document contains a process overview, contact information, relevant foundry source document and a list of supported circuit simulators with versions. The second part includes a classification of the models so you can quickly determine the type of model.
It includes general extraction information, model validation procedures, statistical variation, considerations for noise and matching (if applicable), and a summary/inventory of the measured vs. simulated results plots for each device. The third part divides device-specific data into active (MOS and BJT) and passive (diode, varactor, inductor, capacitor and resistor) extraction and models.