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Agenda
Wednesday, September 24, 2008
| Time |
Event |
| 8:00 a.m. |
Registration |
| 9:00 a.m. |
Welcome Address
Lisa Tafoya, Vice President, Global Research, GSA
|
| 9:15 a.m. |
Keynote Address: Semiconductor Intellectual Property: The Key to a $100 Billion Market
Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
|
| 10:00 a.m. |
Presentation: Challenges, Consumer Demands and Value-Added Solutions -
A Design Community Perspective
Ken Tallo, Director of External IP & Virtual Platforms, Intel Corporation
|
| 10:30 a.m. |
Networking Break |
| 11:00 a.m. |
Presentation: Can Foundries Provide Value to Electronics Companies?
Walter Ng, Vice President, Design Enablement Alliances, Chartered Semiconductor Manufacturing Inc.
|
| 11:30 a.m. |
Presentation:
Reuse is Surging The Why, How and What?
Adam Traidman, Group Marketing Director, Cadence Design Systems, Inc.
|
| 12:00 p.m. |
Presentation:
Realizing the Benefits of IP Within Your Design Environment
John Chilton, Senior Vice President, Marketing and Corporate Development,
Synopsys, Inc.
|
| 12:30 p.m. |
Networking Lunch |
| |
Track 1 |
Track 2 |
| 1:30 p.m. |
Panel Discussion:
Expanding Decreasing Margins: Facilitating Improved Margins, Lower Cost and Faster Time-To-Market
Moderator: Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
Panelists:
John Chilton, Senior Vice President, Marketing and Corporate Development, Synopsys, Inc.
Walter Ng, Vice President, Design Enablement Alliances, Chartered Semiconductor Manufacturing Inc.
Ken Tallo, Director of External IP & Virtual Platforms, Intel Corporation
Adam Traidman, Group Marketing Director, Cadence Design Systems, Inc. |
Panel Discussion: Is Silicon Validation of IP Sufficient?
Moderator: Nitin Deo, Group Director, Cadence Design Systems, Inc.
Panelists:
Dr. Wayne Dai, Chief Executive Officer, VeriSilicon, Inc.
Robert Heaton, Director Analog Solutions Architecture, MIPS Technologies, Inc.
Ming Hsu, Vice President, Worldwide IP Support, UMC
Kamalesh Ruparel, Vice President and General Manager, ASIP Solutions, Virage Logic |
| 2:30 p.m. |
Presentation: Benchmarking - Making IP an Important Part of Your Business Strategy
Glenn Raskin,
Director Program Manager, Qualcomm
|
Panel Discussion:
How Does IP Quality, Verification and Reliability Relate to Yield?
Moderator: Ann Steffora-Mutschler, Senior Editor, EDN
Panelists:
Kurt Wolf, Director, IP Supplier Management Program, TSMC
Dr. Yervant Zorian, Vice President and Chief Scientist, Virage Logic Corporation |
| 3:15 p.m. |
Networking Break |
| 3:30 p.m. |
Presentation: Using Hard IP Quality Risk Assessment Tool to Measure IP: Two Examples of Case Studies - Hard IP Blocks
David Schwan, Engineering Manager, CAD and Layout, RFMD
|
Presentation: How Do I Ensure That any Software Will Work in My SoC?
Marc Greenberg, Director of Technical Marketing, Denali Software, Inc.
|
| 4:15 p.m. |
Presentation:
Soft IP in Mobile Handsets
Oliver Gunasekara, Vice President,
Mobile Business, W & W Communications
|
Presentation: The High Return on Investment for Embedded Non-Volatile Memory
Craig Rawlings, Director of Marketing, Kilopass Technology, Inc.
|
| 5:00 p.m. |
Networking Cocktail Reception |
Thursday, September 25, 2008
| Time |
Event |
| 8:00 a.m. |
Registration |
| 9:00 a.m. |
Welcome Address
Lisa Tafoya, Vice President, Global Research, GSA
|
| 9:15 a.m. |
Keynote Address: IP in the SoC Era: Truth & Consequences
Ron Collett,
President and Chief Executive Officer, Numetrics Management Systems, Inc.
|
| 10:15 a.m. |
Presentation: Do We Need Unified IP Standards?
Dennis Brophy, Vice Chair, Accellera
|
| |
Track 1 |
Track 2 |
| 11:15 a.m. |
Panel Discussion:
Understanding and Utilizing a Compatible IP Ecosystem
Moderator: Ana M. Hunter, Vice President, Samsung Semiconductor
Panelists:
William Billowitch, Director of Marketing, Cadence Design Systems, Inc.
Dr. Jaushin Lee, Chief Executive Officer and President, Imera
Kalar Rajendiran, Senior Director of Marketing, eSilicon Corporation
Warren Savage, Chief Executive Officer, IPextreme
|
Presentation: Creating Best Practices From a Silicon Testing Standpoint
Martin Niset,
Product and Test Engineering Manager, Virage Logic
|
| 12:00 p.m. |
Networking Lunch |
| 1:00 p.m. |
Presentation:
Reducing Hidden Costs in the IP Ecosystem: Where?, When?, How?
Raminderpal Singh,
Senior Technical Staff Member,
Semiconductor Industry Analyst,
IBM Corporate Marketing
|
Panel Discussion:
What Key Issues and Drivers are Considered When Migrating a Design From One Node to the Next?
Moderator: Ron Wilson, Executive Editor, EDN
Panelists:
Rob Aitken, ARM Fellow, ARM
Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys, Inc.
John Maneatis, President, True Circuits, Inc.
Emannuel Riou, RF Engineering Manager, Wipro NewLogic |
| 1:45 p.m. |
Panel Discussion:
IP Responsibility . . .
The Impact of IP Quality on Time-To-Revenue
Moderator: Kurt Wolf, Director, IP Supplier Management Program, TSMC
Panelist:
Charles Janac, President and Chief Executive Officer, Arteris
Gary Ruggles, Director of Sales, Snowbush IP, A Division of Gennum
Mahesh Tirupattur, Executive Vice President, Analog Bits, Inc.
Katty Van Mele, Director Strategic Alliances, Sarnoff Europe BVBA
|
Presentation: RDR in the IP Space - Design Methods and Their Impact on IP
Lars Liebmann, Distinguished Engineer, IBM Corporation
|
| 2:30 p.m. |
Closing Remarks/Panel Discussion
Integration of Foundry and IP Suppliers
Moderator: Dave Bursky, Semiconductor Editor,
Chip Design Magazine
Panelists:
Joe Abler,
Program Manager, Common Platform Ecosystem Enablement, IBM Systems & Technology Group, Semiconductor Solutions, IBM Corporation
Ron Burns, General Manager - Semiconductor and Systems, Wipro Technologies
Tom Lantzsch, Vice President, Marketing, Physical IP, ARM
Massimo Verita, Vice President, Customer Engineering, eASIC Corporation |
| 3:30 p.m. |
Conclude |
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