3D-IC Packaging Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • Projects
  • News


What's New in this Group?

As geometries continue to shrink and 2D scaling becomes increasingly difficult, 3D-IC packaging becomes a natural alternative to continued advances in ever smaller footprints; it is the convergence of performance, power, and functionality. Many of the benefits of 3D-IC packaging, such as increasing complexity while simultaneously improving performance, reducing power consumption, and decreasing footprints are proven and readily understood.  Other benefits such as improving time-to-market, lowering risk, and lowering cost will be conquered as 3D-IC packaging becomes a commercially viable solution across many application domains.


To be the acknowledged industry leader in 3D-IC packaging discussions, ecosystem development, and information dissemination, in order to accelerate the adoption and commercialization of 3D-IC packaging technology.


To provide a neutral, non-competitive forum for industry leaders to openly discuss widespread utilization of 3D-IC packaging technology; encouraging companies to represent their interests while helping to stimulate and shape the adoption of this technology.

  • Provide an avenue for idea exchange and discussion of the technical and commercial needs driving 3D-IC adoption; provide an educational forum.
  • Provide a forum for companies to present their accomplishments and solicit guidance for resolution to specific challenges, as well as discuss relevant and alternative solutions to 3D-IC packaging.
  • Provide industry guidance on emerging 3D-IC packaging fabrication, assembly, and test trends.
  • Understand and provide industry guidance for thermal, ESD, and test impact related to 3D-IC packaging adoption.

Contact Information

Harrison Beasley
Director, Technology

Working Group Chair
Ravi Gutala, SMTS, Altera

Meeting Schedule

What's New in this Group?

3D-IC Packaging

Q4 2015 Meeting

Date: October 21, 2015
Time: 2- 5 p.m.
Location: eSilicon, San Jose, CA

The Great Miniaturization: Systems and Packaging” November 10-11, 2015
Santa Clara, CA.; Presented by MEPTEC and SEMI
Device integration, and especially advanced packaging, drive electronic systems personal mobility – in your pocket, on your wrist, inside your body, in your home, in your car dashboard, almost everywhere. These systems must sense, collect and process data, communicate, and manage its use of power. As these electronics proliferate, highly-integrated electronic systems all the way to the cloud must accommodate this tsunami of data produced by mobile, wearable, and remote sensing. Packaging technologies, manufacturing solutions, as well as the business models that support production, must evolve to meet the challenges that this new era of mobile miniaturization will produce.

Q1 2016 Meeting

Date: January 20, 2016
Time: 2 – 5 p.m.
Location: Zuken, Milpitas, CA

Q2 2016 Meeting

Date: April 20, 2016
Time: 2 – 5 p.m.
Location: San Jose; Host TBD

Q3 2016 Meeting

Date: July 20, 2016
Time: 2 – 5 p.m.
Location: San Jose; Host TBD


What's New in this Group?

Jul 15, 2015

Apr 14, 2015

Jan 21, 2015

Oct 22, 2014

Jul 23, 2014

Apr 9, 2014

Jan 22, 2014

Oct 16, 2013

Jul 17, 2013

Apr 17, 2013

 Jan 23, 2013

Nov 7, 2012

Oct 24, 2012

Jul 12, 2012

Jul 11, 2012

Apr 26, 2012

Dec 12, 2011

Oct 19, 2011


What's New in this Group?
2015 Meeting Minutes
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes


What's New in this Group?

3D-IC Packaging brings many new considerations into play.  All are of course critical, so the working group chose to tackle some of these hurdles by deep exploration and analysis leading to guidelines / tools for the development community.

Our first effort, GSA-ESDA-3D-IC_ESD_Whitepaper provides insight and guidance to Electrostatic Discharge (ESD) differences in stacked 3D-IC, when compared to single die ESD design, and assembly-test.

GSA  member companies, the ESD Association, and academia worked together to produce this whitepaper.  Your feedback is welcomed.

Interested parties may contact hbeasley@gsaglobal.org


What's New in this Group?

PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
3D InCites
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.


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