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Home » Working Groups » 3D-IC Working Group

3D-IC Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • News
  • Projects

Overview

What's New in this Group?

As geometries continue to shrink and 2D scaling becomes increasingly difficult, 3D IC becomes the natural evolution of semiconductor technology; it is the convergence of performance, power, and functionality. Many of the benefits of 3D ICs, such as increasing complexity while simultaneously improving performance, reducing power consumption, and decreasing footprints are proven and readily understood.  Other benefits such as improving time-to-market, lowering risk, and lowering cost will be conquered as 3D ICs becomes a commercially viable solution across many application domains.

Vision

To be the acknowledged industry leader in 3D IC discussion, ecosystem development, and information dissemination, in order to accelerate the adoption and commercialization of 3D IC technology.

Mission

To provide a neutral, non-competitive forum for industry leaders to openly discuss widespread utilization of 3D IC technology; encouraging companies to represent their interests while helping to stimulate and shape the adoption of 3D IC technology.

Objectives
  • Provide an avenue for idea exchange and discussion of the technical and commercial needs driving 3D IC adoption; provide an educational forum.
  • Provide a forum for companies to present their accomplishments and solicit guidance for resolution to specific challenges, as well as discuss relevant and alternative solutions to 3D IC such as 2.5D, FD-SOI, FinFETS, and other CMOS advances.
  • Provide industry guidance on emerging 3D IC fabrication, assembly, and test trends.
  • Understand and provide industry guidance for thermal, ESD, and test impact related to 3D IC adoption.
  • Provide an interactive, online portal that allows the membership to find and utilize information related to 3D IC development activity.

Contact Information

Harrison Beasley
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Ken Potts, Group Director of Marketing, Strategic Planning, Cadence Design Systems

Meeting Schedule

What's New in this Group?
Q3 2013 Meeting

3D IC Working Group
Date: July 17, 2013
Time: 2 – 5 p.m.
Location: Rambus, Sunnyvale, CA
Theme: Cost Reducing 3D IC Development

Click for Overview and Registration

Q4 2013 Meeting

3D IC Working Group
Date: October 23, 2013
Time: 2- 5 p.m.
Location: Silicon Valley

Q1 2014 Meeting

3D IC Working Group
Date: January 22, 2014
Time: 2 – 5 p.m.
Location:  Silicon Valley

Q2 2014 Meeting

3D IC Working Group
Date: April, 2014
Time: 2 – 5 p.m.
Location: Silicon Valley

Presentations

Apr 17, 2013

 Jan 23, 2013

Nov 7, 2012

Oct 24, 2012

Jul 12, 2012

Jul 11, 2012

Apr 26, 2012

Dec 12, 2011

Oct 19, 2011

Minutes

What's New in this Group?
2013 Meeting Minutes
2012 Meeting Minutes

News

What's New in this Group?

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs
Monday, May 20, 2013
3D InCites
WILSONVILLE, Ore., May 20, 2013—Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzaron’s 3D IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.

3D Brings Test Into Fashion
Friday, May 17, 2013
Semiconductor Manufacturing
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

MOSIS joins push for silicon photonics tech
Monday, May 6, 2013
EE Times Asia
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has partnered with ePIXfab, the European Silicon Photonics support centre that offers low-cost prototyping services for photonic ICs. According to the company, the venture gives MOSIS' customers access to Imec's modern fully integrated silicon photonics processes and Tyndall's advanced silicon photonics packaging technology.

Adaptive IP is the wave of the future
Thursday, May 2, 2013
EE Times
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future. More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.

Car, wireless apps push pressure sensors as top MEMS segment
Thursday, April 25, 2013
EE Times Asia
According to the recent prediction from IHS, microelectromechanical system (MEMS) pressure sensors will experience tremendous growth this year to become the leading type of MEMS device. The forecast is driven and hinges on the equally healthy market for automotive and handset markets, noted the market research company.

Parametric Characterization of TSVs
Tuesday, April 23, 2013
Applied Material Blog
Paving the way for the manufacture of 3D-integrated stacked chips, technologists and engineers at Applied Materials have recently completed electrical characterization of through-silicon via (TSV) structures. This development is vitally important since TSVs are the vertical interconnections that carry power and high-bandwidth speed signals between the stacked die of layered logic and memory devices.

3-D interposers stack chips
Friday, April 19, 2013
EE Times
Everybody agrees that three-dimensional (3-D) chip stacks are the future of semiconductor integration, but today the problem of removing heat from the inner layers is daunting, prompting the use of silicon interposers.

Semiconductor PLM – Needs to be smart for techies
Thursday, April 18, 2013
SemiWiki
During my long career in semiconductor, EDA, I have heard, believed and experienced that this is a knowledge industry swamped with rapid innovation and technology drivers; typical manufacturing product development processes like Gantt charts and others do not apply here. The fallback is that most of the time estimations are ad hoc, based on gut-feel or expert opinion. Not only schedule, most of the processes are run by individual preferences; in other words the whole process is more people driven than process driven. Naturally, we see missed targets, re-spins, cost overruns, lost market opportunities and so on. It is said that success rate to first silicon is 0%! And we attribute the Product Lifecycle Management (PLM) issues to high complexity of designs at nanometer scale, high density, analog and digital mixed-signal and so on.

Cavendish Kinetics MEMS Gets Actual Mbps Nearer To Theoretical Mbps
Wednesday, April 17, 2013
Electronics Weekly
Cavendish Kinetics has an answer to the the widening gap between actual mobile data rates and theoretically achievable data rates. GSM in the 90s achieved actual data rates close to the theoretical maxiimum but, ever since, the gap between actual and theoretical has widened. '4G technology supports data rates of 80Mbps,' says Cavendish Kinetics, 'but in practice delivers only 1-8Mbps for many users.'

Going 3D by Evolution Rather Than Revolution: 2.5D, 3D, 5.5D-IC and Beyond
Friday, April 12, 2013
Synopsys
Introduction In 2004, a visionary keynote by STMicroelectronics’ Carlo Cognetti at the Napa KGD Packaging & Test Workshop entitled “Much More than Moore” proposed that “more than Moore” (i.e., the 3D-IC integration of complete, heterogeneous systems in the same package) is complementary to silicon-level integration, which is ruled by the well-known and established “more of Moore”, and suggested that the final result of combining “more than Moore” and “more of Moore” is surprisingly more advanced than what is allowed by the simple progression of the technology nodes. At that time, the road to 3D-IC integration was unclear, R&D engineers at all levels of the supply chain were debating the different options, and 3D-IC was considered a technology of the future. We have made a great deal of progress, and today, 3D-IC integration has become the technology for the future rather than the technology of the future.

TSMC Responds to Samsung!
Friday, April 12, 2013
SemiWiki
This was the 19th annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.

Health consciousness fuels quadruple growth for MEMS sensors
Thursday, April 11, 2013
EE Times
Activity monitors such as the FitLinxx Pebble and Fitbug, for instance, are increasingly finding their way into consumers' hands as employers seek to augment their corporate wellness strategies, noted Shane Walker, senior manager for consumer & digital health research at IHS. "In the United States, this is due in part to the growth of consumer-directed healthcare plans and the Affordable Care Act, which is incentivizing insurers. These corporate programmes are opening yet another channel of distribution for new monitoring devices," he said.

Industry Inches Towards 3D Chips
Monday, April 8, 2013
Semiconductor Design & Manufacturing
GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production. On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

GLOBALFOUNDRIES demonstrates 3D TSV capabilities on 20nm technology
Tuesday, April 2, 2013
Solid State Technology
GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES’ leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.

3D stacking is the future of chip design, says Xilinx
Thursday, March 28, 2013
EE Times Asia
Since the beginning of semiconductor development, chip designers have stuck with Moore's Law, integrating more and more functionality onto their chips. Veteran chip architect Liam Madden, vice president of FPGA development at Xilinx, said during his keynote speech at the annual International Symposium on Physical Systems, that designers can have their 3D cake and eat it, too.

TSMC on Collaboration: JIT Ecosystem Development
Wednesday, March 27, 2013
SemiWiki
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

MEMS pressure sensors in cellphones set to rise to 681M units in 2016
Wednesday, March 20, 2013
Solid State Technology
With the introduction of the Galaxy S4, Samsung Electronics continues to lead the market in the adoption of pressure sensors in smartphones, paving the way for massive growth in the market for these devices in the coming years. Global shipments of microelectromechanical system (MEMS) pressure sensors in cellphones are set to rise to 681 million units in 2016, up more than eightfold from 82 million in 2012, according to the IHS iSuppli MEMS & Sensors Service at information and analytics provider IHS (NYSE: IHS). Shipments this year are expected to double to 162 million units, as presented in the attached figure, primarily due to Samsung’s usage of pressure sensors in the Galaxy S4 and other smartphone models.

A Brief History of the Foundry Industry, part 2
Wednesday, March 13, 2013
SemiWiki
Part 1 here. The line between fabless semiconductor companies and IDMs has blurred over the last decade. Back in the 1990s, most IDMs manufactured most of their own product, perhaps using a foundry for a small percentage of additional capacity when required. But their own manufacturing was competitive, both in terms of the capacity of fab they could afford to build, and in terms of process technology.

The Interposer workshop in Austin
Sunday, March 10, 2013
3D InCites
Did anyone miss the Sound of Music bit during the Oscars? Anyway, with the sounds of “The Hills are alive..” in my head, I drove off the next day down to the Hill Country in Austin to the invitation-only, On The Road to Fine Feature IC Package Substrates and Interposers Workshop, hosted by Jan Vardaman of TechSearch International. This is a nice, comfortable-sized venue with approximately 100 attendees that makes for some very interesting one-on-one conversations.

Flip-chip platform to lift wafer shipments
Wednesday, March 6, 2013
EE Times
The flip-chip platform will grow by threefold over the next five years to reach over 40 million 12" equivalent wafer (eq) start per year, according to research firm Yole Développement.

SSIA: MEMS to go mainstream this year
Thursday, February 21, 2013
EE Times Asia
EE Times Asia reached out to the Singapore Semiconductor Industry Association for their take on market trends and notable technologies to watch out for in 2013. SSIA discusses how the current economic environment is affecting its member companies and the steps it is taking to ensure the continued career growth of electronic engineers in the country.

TSMC ♥ Cadence
Tuesday, February 19, 2013
SemiWiki
In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.

Assertion Synthesis: Atrenta, Cadence and AMD Tell All
Monday, February 11, 2013
SemiWiki
Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta's BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the product.

Want 10nm Wafers? That'll Cost You
Sunday, February 10, 2013
SemiWiki
As you know, I've been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones's "fireside chat".

GloFo, Samsung in race to 14nm
Wednesday, February 6, 2013
EE Times
Globalfoundries and Samsung are in a dead heat to get their first 14 nm production wafers out before the end of the year, aiming to beat rival Taiwan Semiconductor Manufacturing Co. by as much as a year. Meanwhile, an IBM building in New York sits empty, waiting for an extreme ultraviolet (EUV) lithography machine to light the way to the industry’s longer-term future.

HOME | OLDER HEADLINES

Projects

The 3D IC working group has two projects underway, with plans for others as resources permit.  These projects are intended to provide an updated 3D IC Roadmap, leading to an online, interactive portal in the future.  We are also developing a guide to business models: What flows are developing for wafer testing, and die assembly and testing, including final test.

 3D IC Business Models

The goal of this effort is to analyze existing and emerging 2.5D and 3D fabrication, assembly, and Test flows.  There are a larger number of variables in play, and the nuances of each flow are being considered.  The end product will address pros and cons for the most likely dominant flows.

GSA 3D IC Business Model Update

3D IC Almanac

As market pull drives 3D IC adoption, many new companies and products appear.  The goal is this effort is to provide a one-stop location for information related to 3D IC development (companies, products, tools, services).

3D IC Almanac Update

 

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