Mixed-Signal Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • Checklists
  • Projects
  • News


What's New in this Group?

Mixed-Signal technologies are critical components of semiconductor development. Real world data is inherently analog in nature and must be converted to digital signals for computational analysis. Fueled by tremendous advancements in process technologies,  mixed signal applications are among the fastest growing market segments within the semiconductor industry today. But with these advanced process technologies come new challenges to mixed signal design: analog-digital co-design, functional verification, test, and modeling on the technical side and resource management and collaboration among design teams and partners on the human side.


Promote the discussion, information exchange, and collaboration impacting both the technical and the human resource challenges that the AMS industry is facing, in order to have a positive impact on industry growth and profitability.


Provide a non-competitive forum for the mixed signal community to explore and discuss critical aspects of successful implementation including scaling, integration, DFM, verification, test, and power efficiencies and identify key elements that can improve efficiencies, design productivity, and profitability.

  • Improve the development environment through joint efforts leading to widespread adoption of interoperable PDK.
  • Generate mixed signal specific checklists that improve user understanding of foundry offerings and needs (PDK, PCM, …), while minimizing errors and improving interaction between foundries and fabless designers.
  • Discuss novel and creative approaches to closing the gap between digital and analog design.
  • Identify opportunities for enhanced integration and modularization capability: advanced packaging, SoCs, MEMS, etc.
  • Explore improved modeling techniques, such as RF Modeling, Analog Modeling with FinFET technology.

Contact Information

Harrison Beasley
Director, Technology
E hbeasley@gsaglobal.org

Working Group Chair
Dr. Abhijit Gupta, Director, Foundry Technology, SanDisk

Meeting Schedule

What's New in this Group?
Q1 2015 Meeting

MS Working Group
Date: February 18, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley

Overview & Registration

Q2 2015 Meeting

MS Working Group
Date: May 20, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley

Q3 2014 Meeting

MS Working Group
Date: August 19, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley

Q5 2015 Meeting

MS Working Group
Date: November 11, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley


What's New in this Group?
February 19, 2015
November 12, 2014
August 20, 2014
May 7, 2014
February 20, 2014
  • AMS WG Overview (PDF, 446 KB) /  Abhijit Gupta, SanDisk
  • The Future of Mixed-Signal Verification  Helene Thibieroz, Synopsys
  • Mixed-Signal IP Verification on Advanced Process Nodes, Bob Lefferts, Synopsys
November 14, 2013
August 21, 2013
May 15, 2013
February 13, 2013
November 14, 2012
November 7, 2012
August 22, 2012
May 21, 2012


What's New in this Group?
2015 Meeting Minutes
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes


 What's New in this Group?
PDK Quality Checklist and User’s Guide

Checklist is completed by the PDK developer and delivered with each new release of an Mixed Signal PDK. This checklist will allow  design teams and foundries to more easily communicate needs, capabilities, and expectations for process PDKs.  This document helps obtain a better understanding of the source data, completeness and quality of the PDK before using it to design IC or to modify it to fit into your in-house design flow.  The Checklist Users Guide has been combined with the checklist, in Version 4.0 (July 2013)

MS/RF Process Control Monitoring (PCM) Checklist

Provides a recommended list of parameters that foundries should measure (i.e., test); a uniform way to measure each parameter (i.e., describe the measurement); and a consistent way to describe the test data.

MS/RF Process Checklist

Identifies the different elements of a foundry’s AMS/RF process and its ability to fulfill a semiconductor company’s needs; it serves as a basic set of guidelines for measuring available items in an AMS/RF foundry process; and it is an efficient way to communicate information in a consistent format across all foundries.

Mixed-Signal/RF SPICE Model Checklist

A document completed by the SPICE model developer and delivered with each new release of an SPICE model. This document helps developers better understand the source data, completeness and quality of the model before using it to design ICs or to re-extract it to fit into specific product needs. A Checklist Users Guide and Checklist Taxonomy & Definitions are also available for download.


What's New in this Group?
Designing for Mixed-Signal Foundry Interoperability

The working group analyzed tool support for schematic and layout migration of mixed signal circuits to new process nodes or a different foundry.  This paper summarizes the tools evaluated and provides a comparison table, allowing the mixed signal designer to determine which tool best supports their needs.

Presentations to Project Team:

June 23, 2014

May 7, 2014

Apr 16, 2014

To participate in biweekly teleconferences, contact hbeasley@gsaglobal.org

Foundry Interoperability can be thought of as the ability to port a design from one foundry PDK to another foundry PDK at the same process node.

With the capability to more easily migrate, or to design for Foundry Interoperability, design teams stand to gain by using fewer resources for migration, enabling a faster time to market, and having the ability to more cost effectively second source products.

Foundries also benefit with less customer support for migration, faster time to tapeout, and lower threshold to design wins.  IP providers can support multiple foundries with fewer resources.

Building on the standardized PDK effort, this project team is performing a thorough analysis of existing tools capability and working with foundries to identify gaps.  The end goal is make design migration as simple as possible, by providing the industry with existing tools analysis, and a path to enhanced capability.

The Analog / Mixed Signal working group has released the following documents.

1)  Motivation for Using Standardized PDK

This paper addresses PDK standardization efforts, including  iPDK and OpenPDK.  We address the goals of each effort, as well as commonality and deltas between them.  The business case for and obstacles to using a standardized PDK are presented.   We postulate the impact on foundries, fabless designers, and EDA vendors.

2)  PDK (Process Development Kit) Quality Checklist & User’s Guide

The PDK Quality Checklist and User’s Guide is an enhanced update to the 2008 GSA PDK Checklist.  This document is completed by the PDK developer and delivered with each new release of an Analog / Mixed Signal / RF PDK. This checklist will allow  design teams and foundries to more easily communicate needs, capabilities, and expectations for process PDKs.


What's New in this Group?

PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
3D InCites
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.

MEMS treads logic road
Wednesday, August 6, 2014
EETimes Asia
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.

TSMC Details Family of Chip Stacks
Thursday, April 24, 2014
EE Times
TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations. The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.

3D EDA brings together proven 2D solutions
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year. "This is unprecedented," said Kelvin Low, senior director of marketing at Samsung. "It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model," he added. Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

Fast & Accurate Thermal Analysis of 3D-ICs
Monday, April 14, 2014
As Moore's law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it's extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, Tmax control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.

FinFET Custom Design
Wednesday, April 2, 2014
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.


Bookmark the permalink.