Analog / Mixed-Signal Working Group

Overview

Analog / Mixed-Signal (AMS) technologies are critical components of semiconductor development. Real world data is inherently analog in nature and must be converted to digital signals for computational analysis. Fueled by tremendous advancements in process technologies,  mixed signal applications are among the fastest growing market segments within the semiconductor industry today. But with these advanced process technologies come new challenges to mixed signal design: analog-digital co-design, functional verification, test, and modeling on the technical side and resource management and collaboration among design teams and partners on the human side.

Vision

Promote the discussion, information exchange, and collaboration impacting both the technical and the human resource challenges that the AMS industry is facing, in order to have a positive impact on industry growth and profitability.

Mission

Provide a non-competitive forum for the AMS community to explore and discuss critical aspects of successful AMS  implementation including scaling, integration, DFM, verification, test, and power efficiencies and identify key elements that can improve efficiencies, design productivity, and profitability.

Objectives

• Improve AMS development environment through joint efforts leading to widespread adoption of interoperable PDK.
• Generate AMS checklists that improve user understanding of foundry offerings and needs (PDK, PCM, …), while minimizing errors and improving interaction between foundries and fabless designers.
• Discuss novel and creative approaches to closing the gap between digital and analog design.
• Identify opportunities for enhanced integration and modularization capability: advanced packaging, SoCs, MEMS, etc.
• Explore improved modeling techniques, such as RF Modeling, Analog Modeling with FinFET technology.

Contact Information

Harrison Beasley
972.489.0248
E hbeasley@gsaglobal.org

AMS Working Group Chair
Dr. Abhijit Gupta, Director, Foundry Technology, SanDisk

Meeting Schedule

Q3 2013 Meeting

AMS Working Group
Date: August 21, 2013
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley
Theme: AMS Verification

Q4 2013 Meeting

AMS Working Group
Date: November 20, 2013
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley

Q1 2014 Meeting

AMS Working Group
Date: February 19, 2014
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley

Q2 2012 Meeting

AMS Working Group
Date: May 21, 2014
Time: 2:00 p.m. – 5:00 p.m.
Location: Cadence, 2665 Seely Ave, San Jose, CA
Theme: Open Access Implementation
Speakers: Cadence

Presentations

Meeting:	AMS Working Group
Date:	May 15, 2013
Location:	Cadence, San Jose, CA
Presentations:	AMS Working Group Overview (PDF, 445 KB) Harrison Beasley, GSA Cadence & Open Access (PDF, 2,279 KB) Mladen Nizic, Cadence PDK Whitepaper Update  (PDF, 264 KB) Jim Culp, IBM

 

Meeting:	AMS Working Group
Date:	February 13, 2013
Location:	Mentor Graphics, Fremont, CA
Presentations:	AMS Working Group Overview (PDF, 455 KB) Dr. Abhijit Gupta, SanDisk Mentor AMS Design Kit Status (PDF, 1,940 KB) Linda Fosler, Mentor Graphics IPL and iPDK Overview GSA Feb 2013 (PDF, 395 KB) Jingwen Yuan, President IPL Alliance, Synopsys Open PDK Update (PDF, 369 KB) Jim Culp, IBM

 

Meeting:	AMS Working Group
Date:	November 14, 2012
Location:	Microsemi, San Jose, CA
Presentations:	AMS Working Group Overview (PDF, 701 KB) Dr. Abhijit Gupta, SanDisk Statistical Corners for Accurate Nanometer-Scale AMS Characterization (PDF, 241 KB) Paul Estrada, COO, Berkeley Design Automation Options for Using the Right Technologies for Performance in an SoC Jim Aralis, Microsemi MOS-AK / GSA Working Group Overview (PDF, 2902 KB) Wladek Grabinski, EPFL

 

Meeting:	Technology Steering Committee – Working Group Review
Date:	November 7, 2012
Location:	Cavium, San Jose, CA
Presentations:	AMS Working Group Update (PDF, 225 KB) Dr. Abhijit Gupta, SanDisk

 

Meeting;	AMS Working Group
Date:	August 22, 2012
Location:	SanDisk, Milpitas, CA
Presentations:	Introductions and Overview (PDF, 612 KB) Dr. Abhijit Gupta, SanDisk Addressing AMS Design Challenges in Advanced Technology Nodes (PDF, 230 KB) Prasad Subramaniam, eSilicon Challenges Of RF Transceiver Design in Advanced CMOS Nodes (PDF, 1847 KB) Sanjay Moghe, RFIC Solutions

 

Meeting:	AMS Working Group
Date:	May 21, 2012
Location:	Intersil, Milpitas, CA
Presentations:	Introductions and Overview Harrison Beasley, GSA GSA AMS Working Group History Harrison Beasley, GSA Analog / Mixed Signal – A Sandisk Perspective Dr. Abhijit Gupta, SanDisk

 

Minutes

2013 Meeting Minutes

• FEB 13, 2013 Working Group Minutes  (PDF, 765 KB)
• JAN 9, 2013 Core Team Minutes  (PDF, 763 KB)

2012 Meeting Minutes

• NOV 14, 2012 Working Group Minutes  (PDF, 758 KB)
• OCT 24, 2012 Core Team Minutes  (PDF, 751 KB)
• AUG 27, 2012 Working Group Minutes  (PDF, 867 KB)
• JUN 21, 2012 Working Group Minutes (PDF, 800 KB)

Checklists

AMS/RF Process Control Monitoring (PCM) Checklist

Provides a recommended list of parameters that foundries should measure (i.e., test); a uniform way to measure each parameter (i.e., describe the measurement); and a consistent way to describe the test data.

AMS/RF Process Checklist

Identifies the different elements of a foundry’s AMS/RF process and its ability to fulfill a semiconductor company’s needs; it serves as a basic set of guidelines for measuring available items in an AMS/RF foundry process; and it is an efficient way to communicate information in a consistent format across all foundries.

Mixed-Signal/RF PDK Checklist

A document completed by the process design kit (PDK) developer and delivered with each new release of a mixed-signal/RF PDK. This document helps obtain a better understanding of the source data, completeness and quality of the PDK before using it to design ICs or to modify it to fit into your in-house design flow. A Checklist Users Guide is also available for download.

Mixed-Signal/RF SPICE Model Checklist

A document completed by the SPICE model developer and delivered with each new release of an SPICE model. This document helps developers better understand the source data, completeness and quality of the model before using it to design ICs or to re-extract it to fit into specific product needs. A Checklist Users Guide and Checklist Taxonomy & Definitions are also available for download.

News

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs
Monday, May 20, 2013
3D InCites
WILSONVILLE, Ore., May 20, 2013—Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzaron’s 3D IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.

3D Brings Test Into Fashion
Friday, May 17, 2013
Semiconductor Manufacturing
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

MOSIS joins push for silicon photonics tech
Monday, May 6, 2013
EE Times Asia
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has partnered with ePIXfab, the European Silicon Photonics support centre that offers low-cost prototyping services for photonic ICs. According to the company, the venture gives MOSIS' customers access to Imec's modern fully integrated silicon photonics processes and Tyndall's advanced silicon photonics packaging technology.

Adaptive IP is the wave of the future
Thursday, May 2, 2013
EE Times
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future. More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.

Car, wireless apps push pressure sensors as top MEMS segment
Thursday, April 25, 2013
EE Times Asia
According to the recent prediction from IHS, microelectromechanical system (MEMS) pressure sensors will experience tremendous growth this year to become the leading type of MEMS device. The forecast is driven and hinges on the equally healthy market for automotive and handset markets, noted the market research company.

3-D interposers stack chips
Friday, April 19, 2013
EE Times
Everybody agrees that three-dimensional (3-D) chip stacks are the future of semiconductor integration, but today the problem of removing heat from the inner layers is daunting, prompting the use of silicon interposers.

Semiconductor PLM – Needs to be smart for techies
Thursday, April 18, 2013
SemiWiki
During my long career in semiconductor, EDA, I have heard, believed and experienced that this is a knowledge industry swamped with rapid innovation and technology drivers; typical manufacturing product development processes like Gantt charts and others do not apply here. The fallback is that most of the time estimations are ad hoc, based on gut-feel or expert opinion. Not only schedule, most of the processes are run by individual preferences; in other words the whole process is more people driven than process driven. Naturally, we see missed targets, re-spins, cost overruns, lost market opportunities and so on. It is said that success rate to first silicon is 0%! And we attribute the Product Lifecycle Management (PLM) issues to high complexity of designs at nanometer scale, high density, analog and digital mixed-signal and so on.

Cavendish Kinetics MEMS Gets Actual Mbps Nearer To Theoretical Mbps
Wednesday, April 17, 2013
Electronics Weekly
Cavendish Kinetics has an answer to the the widening gap between actual mobile data rates and theoretically achievable data rates. GSM in the 90s achieved actual data rates close to the theoretical maxiimum but, ever since, the gap between actual and theoretical has widened. '4G technology supports data rates of 80Mbps,' says Cavendish Kinetics, 'but in practice delivers only 1-8Mbps for many users.'

Going 3D by Evolution Rather Than Revolution: 2.5D, 3D, 5.5D-IC and Beyond
Friday, April 12, 2013
Synopsys
Introduction In 2004, a visionary keynote by STMicroelectronics’ Carlo Cognetti at the Napa KGD Packaging & Test Workshop entitled “Much More than Moore” proposed that “more than Moore” (i.e., the 3D-IC integration of complete, heterogeneous systems in the same package) is complementary to silicon-level integration, which is ruled by the well-known and established “more of Moore”, and suggested that the final result of combining “more than Moore” and “more of Moore” is surprisingly more advanced than what is allowed by the simple progression of the technology nodes. At that time, the road to 3D-IC integration was unclear, R&D engineers at all levels of the supply chain were debating the different options, and 3D-IC was considered a technology of the future. We have made a great deal of progress, and today, 3D-IC integration has become the technology for the future rather than the technology of the future.

TSMC Responds to Samsung!
Friday, April 12, 2013
SemiWiki
This was the 19th annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.

Health consciousness fuels quadruple growth for MEMS sensors
Thursday, April 11, 2013
EE Times
Activity monitors such as the FitLinxx Pebble and Fitbug, for instance, are increasingly finding their way into consumers' hands as employers seek to augment their corporate wellness strategies, noted Shane Walker, senior manager for consumer & digital health research at IHS. "In the United States, this is due in part to the growth of consumer-directed healthcare plans and the Affordable Care Act, which is incentivizing insurers. These corporate programmes are opening yet another channel of distribution for new monitoring devices," he said.

Industry Inches Towards 3D Chips
Monday, April 8, 2013
Semiconductor Design & Manufacturing
GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production. On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

3D stacking is the future of chip design, says Xilinx
Thursday, March 28, 2013
EE Times Asia
Since the beginning of semiconductor development, chip designers have stuck with Moore's Law, integrating more and more functionality onto their chips. Veteran chip architect Liam Madden, vice president of FPGA development at Xilinx, said during his keynote speech at the annual International Symposium on Physical Systems, that designers can have their 3D cake and eat it, too.

TSMC on Collaboration: JIT Ecosystem Development
Wednesday, March 27, 2013
SemiWiki
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

A Brief History of the Foundry Industry, part 2
Wednesday, March 13, 2013
SemiWiki
Part 1 here. The line between fabless semiconductor companies and IDMs has blurred over the last decade. Back in the 1990s, most IDMs manufactured most of their own product, perhaps using a foundry for a small percentage of additional capacity when required. But their own manufacturing was competitive, both in terms of the capacity of fab they could afford to build, and in terms of process technology.

The Interposer workshop in Austin
Sunday, March 10, 2013
3D InCites
Did anyone miss the Sound of Music bit during the Oscars? Anyway, with the sounds of “The Hills are alive..” in my head, I drove off the next day down to the Hill Country in Austin to the invitation-only, On The Road to Fine Feature IC Package Substrates and Interposers Workshop, hosted by Jan Vardaman of TechSearch International. This is a nice, comfortable-sized venue with approximately 100 attendees that makes for some very interesting one-on-one conversations.

Flip-chip platform to lift wafer shipments
Wednesday, March 6, 2013
EE Times
The flip-chip platform will grow by threefold over the next five years to reach over 40 million 12" equivalent wafer (eq) start per year, according to research firm Yole Développement.

SSIA: MEMS to go mainstream this year
Thursday, February 21, 2013
EE Times Asia
EE Times Asia reached out to the Singapore Semiconductor Industry Association for their take on market trends and notable technologies to watch out for in 2013. SSIA discusses how the current economic environment is affecting its member companies and the steps it is taking to ensure the continued career growth of electronic engineers in the country.

TSMC ♥ Cadence
Tuesday, February 19, 2013
SemiWiki
In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.

Assertion Synthesis: Atrenta, Cadence and AMD Tell All
Monday, February 11, 2013
SemiWiki
Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta's BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the product.

GloFo, Samsung in race to 14nm
Wednesday, February 6, 2013
EE Times
Globalfoundries and Samsung are in a dead heat to get their first 14 nm production wafers out before the end of the year, aiming to beat rival Taiwan Semiconductor Manufacturing Co. by as much as a year. Meanwhile, an IBM building in New York sits empty, waiting for an extreme ultraviolet (EUV) lithography machine to light the way to the industry’s longer-term future.

Could “Less than Moore” be better to support Mobile segment explosion?
Tuesday, February 5, 2013
SemiWiki
If you take a look at the explosion of the Mobile segment, linked with the fantastic world-wide adoption of smartphone and media tablet, you clearly see that the SC industry evolution during –at least- the next five years will be intimately correlated with the mobile segments. Not really a surprise, but the question I would like to raise is: “will this explosion of SC revenue in mobile segment will only be supported be applying Moore’ law (race for integration, more and more functionalities in a single chip targeting the most advanced technology nodes), or could we imagine that some subsequent mobile sub-segment could be served by less integrated solution, offering much faster TTM and finally better business model and more profit?”

European 3D TSV Summit: But Wait, There’s More!
Tuesday, February 5, 2013
3D InCites
Day Two of the European 3D TSV Summit dawned bright and clear, with such a spectacular view of the nearby French Alps that it took real commitment to stay indoors and focus on the task at hand. But I have to admit that for the most part, it was worth the sacrifice to hear what this collection of speakers had to say.

Mentor @ the TSMC Open Innovation Platform Forum
Wednesday, January 16, 2013
SemiWiki
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.

2013 Predictions for 3D ICs as told by Everyone - Part 2
Tuesday, January 15, 2013
3D InCites
No sooner did I post last week’s curation of predictions for the semiconductor industry, and particularly for 3D ICs, than several more popped up online. I suspect this type of thing to continue for the next few weeks, and I will try and continue to cherry-pick the ones that made reference to 3D integration.

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Projects

The Analog / Mixed Signal working group has two projects underway: 1) Standardized PDK (Process Development Kit) Checklist; and 2) updated PCM (Process Control Monitor) Checklist.  As Progress is made on these documents, updates will available by clicking the appropriate link below.

PDK Whitepaper and Quality Checklist

The working group is nearing completion of a whitepaper to address the rationale for using standards-based PDK.  This document addresses the efforts of iPDK and OpenPDK, looking at the goals of each effort, as well as commonality and deltas between each.  The business case and obstacles to using a standardized PDK will be discussed.   Impact on foundries, fabless designers, and EDA vendors will be addressed.

The PDK Quality Checklist is an enhanced update the 2008 GSA PDK Checklist.  This checklist will allow  design teams and foundries to more easily communicate needs, capabilities, and expectations for process PDKs.

Standardized AMS PDK Update

PCM Updates

The working group is reviewing, updating and enhancing the 2008 PCM checklist.   The goal is to define a standard way of communicating basic process parameters and criteria for mixed-signal/RF processes and to develop standard definitions for quantitative and qualitative metrics that can be used for classification and as figures of merit in selecting an appropriate process and process options for a specific design application.

PCM Checklist Overview

Draft PCM Checklist