- Meeting Schedule
Mixed-Signal technologies are critical components of semiconductor development. Real world data is inherently analog in nature and must be converted to digital signals for computational analysis. Fueled by tremendous advancements in process technologies, mixed signal applications are among the fastest growing market segments within the semiconductor industry today. But with these advanced process technologies come new challenges to mixed signal design: analog-digital co-design, functional verification, test, and modeling on the technical side and resource management and collaboration among design teams and partners on the human side.
Promote the discussion, information exchange, and collaboration impacting both the technical and the human resource challenges that the AMS industry is facing, in order to have a positive impact on industry growth and profitability.
Provide a non-competitive forum for the mixed signal community to explore and discuss critical aspects of successful implementation including scaling, integration, DFM, verification, test, and power efficiencies and identify key elements that can improve efficiencies, design productivity, and profitability.
- Improve the development environment through joint efforts leading to widespread adoption of interoperable PDK.
- Generate mixed signal specific checklists that improve user understanding of foundry offerings and needs (PDK, PCM, …), while minimizing errors and improving interaction between foundries and fabless designers.
- Discuss novel and creative approaches to closing the gap between digital and analog design.
- Identify opportunities for enhanced integration and modularization capability: advanced packaging, SoCs, MEMS, etc.
- Explore improved modeling techniques, such as RF Modeling, Analog Modeling with FinFET technology.
Working Group Chair
Dr. Abhijit Gupta, Director, Foundry Technology, SanDisk
Q3 2015 Meeting
Date: August 19, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: NXP, San Jose, CA
Q4 2015 Meeting
Date: November 11, 2015
Time: 2:00 p.m. – 5:00 p.m.
Location: SanDisk, Milpitas, CA
Q1 2016 Meeting
Date: February 17, 2016
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley
Q2 2016 Meeting
Date: May 18, 2016
Time: 2:00 p.m. – 5:00 p.m.
Location: Silicon Valley
February 19, 2015
- AMS WG Overview (PDF, 452 KB) / Abhijit Gupta, SanDisk
- Bluetooth Smart Solutions (PDF, 1,269 KB) / Michel Behgin, Insight SiP
- Devices, Lithography, Interconnect & Materials (PDF, 2,283 KB) / Jamil Kawa, Synopsys
November 12, 2014
- AMS WG Overview (PDF, 444 KB) / Abhijit Gupta, SanDisk
- Foundry PMIC Technology Trends (PDF, 1,789 KB) / Il Yong Park, GlobalFoundries
- PMIC Technology (TBD) / Rene Jakubasch, IDT
August 20, 2014
- AMS WG Overview (PDF, 447 KB) / Abhijit Gupta, SanDisk
- On-Wafer Probing Best Practices for Power Electronics (PDF, 2,242 KB) Michael Lyman, Cascade Microtech
- Power Technology Applications (PDF, 1,189 KB), Shannon Pu, SMIC
May 7, 2014
- AMS WG Overview (PDF, 449 KB) / Abhijit Gupta, SanDisk
- Design Impact of FinFETs (PDF, 1,107 KB) Carey Roberson, Mentor Graphics
- Physical IP Development on FinFET (PDF, 1,934 KB), Navraj Nandra, Synopsys
- AMS Design Challenges with FinFET, Tom Quan, TSMC
February 20, 2014
- AMS WG Overview (PDF, 446 KB) / Abhijit Gupta, SanDisk
- The Future of Mixed-Signal Verification Helene Thibieroz, Synopsys
- Mixed-Signal IP Verification on Advanced Process Nodes, Bob Lefferts, Synopsys
November 14, 2013
- AMS WG Overview (PDF, 488 KB) / Harrison Beasley, GSA
- RF Simulation Challenges (PDF, 823 KB) / Tony Zortea, PMC-Sierra
- Foundry Interoperability (PDF, 51 KB) / Abhitit Gupta, SanDisk
August 21, 2013
- AMS WG Overview (PDF, 445 KB) / Abhijit Gupta, SanDisk
- Standardized PDK Whitepaper Released (PDF, 120 KB) / Jim Culp, IBM
- Impact of FinFET Technology on AMS Design (PDF, 1,374 KB) / Gopal Srinivasan, GlobalFoundries
May 15, 2013
- AMS Working Group Overview (PDF, 445 KB) / Abhijit Gupta, SanDisk
- Cadence & Open Access (PDF, 2,279 KB) / Mladen Nizic, Cadence
- PDK Whitepaper Update (PDF, 264 KB) / Jim Culp, IBM
February 13, 2013
- AMS Working Group Overview (PDF, 455 KB) / Dr. Abhijit Gupta, SanDisk
- Mentor AMS Design Kit Status (PDF, 1,9 MB) / Linda Fosler, Mentor Graphics
- IPL and iPDK Overview GSA Feb 2013 (PDF, 395 KB) / Jingwen Yuan, President IPL Alliance, Synopsys
- Open PDK Update (PDF, 369 KB) / Jim Culp, IBM
November 14, 2012
- AMS Working Group Overview (PDF, 701 KB) / Dr. Abhijit Gupta, SanDisk
- Statistical Corners for Accurate Nanometer-Scale AMS Characterization (PDF, 241 KB) / Paul Estrada, COO, Berkeley Design Automation
- MOS-AK / GSA Working Group Overview (PDF, 2902 KB) / Wladek Grabinski, EPFL
November 7, 2012
- AMS Working Group Update (PDF, 225 KB) / Dr. Abhijit Gupta, SanDisk
August 22, 2012
- Introductions and Overview (PDF, 612 KB) / Dr. Abhijit Gupta, SanDisk
- Addressing AMS Design Challenges in Advanced Technology Nodes (PDF, 230 KB) / Prasad Subramaniam, eSilicon
- Challenges Of RF Transceiver Design in Advanced CMOS Nodes (PDF, 1847 KB) / Sanjay Moghe, RFIC Solutions
May 21, 2012
2015 Meeting Minutes
- Feb 18, 2015 Working Group Minutes (PDF, 759 KB)
2014 Meeting Minutes
- NOV 12, 2014 Working Group Minutes (PDF, 757 KB)
- AUG 20, 2014 Working Group Minutes (PDF, 756 KB)
- MAY 7, 2014 Working Group Minutes (PDF, 768 KB)
- FEB 23, 2014 Working Group Minutes (PDF, 760 KB)
2013 Meeting Minutes
- NOV 14, 2013 Working Group Minutes (PDF, 763 KB)
- AUG 21, 2013 Working Group Minutes (PDF, 758 KB)
- FEB 13, 2013 Working Group Minutes (PDF, 765 KB)
- JAN 9, 2013 Core Team Minutes (PDF, 763 KB)
2012 Meeting Minutes
Checklist is completed by the PDK developer and delivered with each new release of an Mixed Signal PDK. This checklist will allow design teams and foundries to more easily communicate needs, capabilities, and expectations for process PDKs. This document helps obtain a better understanding of the source data, completeness and quality of the PDK before using it to design IC or to modify it to fit into your in-house design flow. The Checklist Users Guide has been combined with the checklist, in Version 4.0 (July 2013)
Provides a recommended list of parameters that foundries should measure (i.e., test); a uniform way to measure each parameter (i.e., describe the measurement); and a consistent way to describe the test data.
Identifies the different elements of a foundry’s AMS/RF process and its ability to fulfill a semiconductor company’s needs; it serves as a basic set of guidelines for measuring available items in an AMS/RF foundry process; and it is an efficient way to communicate information in a consistent format across all foundries.
A document completed by the SPICE model developer and delivered with each new release of an SPICE model. This document helps developers better understand the source data, completeness and quality of the model before using it to design ICs or to re-extract it to fit into specific product needs. A Checklist Users Guide and Checklist Taxonomy & Definitions are also available for download.
The working group analyzed tool support for schematic and layout migration of mixed signal circuits to new process nodes or a different foundry. This paper summarizes the tools evaluated and provides a comparison table, allowing the mixed signal designer to determine which tool best supports their needs.
Presentations to Project Team:
June 23, 2014
- Process Migration for Analog and Mixed Signal IP (PDF, 1,691 KB), Tim Regan, IN2FAB
- EDIF File Translation for AMS Design (PPS, 592 KB), Igor Luvishis, Elgris
May 7, 2014
- Full Custom Design Migration (PDF, 2,690 KB), Michael Pronath, MunEDA
Apr 16, 2014
- Cadence – Foundry Interoperability (PDF, 337 KB), Jim McMahon, Cadence
- Sagantec – Foundry Interoperability (PDG, 559 KB), Simon Klaver, Sagantec
To participate in biweekly teleconferences, contact firstname.lastname@example.org
Foundry Interoperability can be thought of as the ability to port a design from one foundry PDK to another foundry PDK at the same process node.
With the capability to more easily migrate, or to design for Foundry Interoperability, design teams stand to gain by using fewer resources for migration, enabling a faster time to market, and having the ability to more cost effectively second source products.
Foundries also benefit with less customer support for migration, faster time to tapeout, and lower threshold to design wins. IP providers can support multiple foundries with fewer resources.
Building on the standardized PDK effort, this project team is performing a thorough analysis of existing tools capability and working with foundries to identify gaps. The end goal is make design migration as simple as possible, by providing the industry with existing tools analysis, and a path to enhanced capability.
The Analog / Mixed Signal working group has released the following documents.
This paper addresses PDK standardization efforts, including iPDK and OpenPDK. We address the goals of each effort, as well as commonality and deltas between them. The business case for and obstacles to using a standardized PDK are presented. We postulate the impact on foundries, fabless designers, and EDA vendors.
2) PDK (Process Development Kit) Quality Checklist & User’s Guide
The PDK Quality Checklist and User’s Guide is an enhanced update to the 2008 GSA PDK Checklist. This document is completed by the PDK developer and delivered with each new release of an Analog / Mixed Signal / RF PDK. This checklist will allow design teams and foundries to more easily communicate needs, capabilities, and expectations for process PDKs.
PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).
Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.
Litho Options Sparse After 10nm
Thursday, October 16, 2014
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.
200mm fabs: Older but thriving
Wednesday, October 15, 2014
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.
Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.
MEMS treads logic road
Wednesday, August 6, 2014
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.