Intellectual Property Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • Tools
  • Projects
  • News

Overview

What's New in this Group?

Intellectual Property (IP) is a cornerstone of the semiconductor industry.  Semiconductor companies generate, buy, and sell IP cores as a normal course of business.  Many companies have been purchased based solely on the value of their IP.  Additionally, patent rights are regularly traded between industry companies. However, issues abound with the purchase of IP in terms of understanding the actual IP content, licensing terms, royalty payments, etc..  Similarly, IP sellers strive to provide IP that is viable for a broad user base.

Vision

Provide a forum for open discussion of intellectual property best practices, licensing trends, sourcing / supplying, and process improvements.

Mission

Provide industry education relevant to IP Licensing, IP reuse, IP roadmaps.  Understand IP trends through timely surveys and analysis.

Objectives
  • Periodic IP Licensing best practices survey and analysis
  • Improve IP strategies by applying metrics that align buyers and sellers on key success indicators
  • Identify IP sourcing process advances and provide community education
  • Generate creative ideas to source IP to start-ups, envision IP as a product, and provide guidance on IP roadmaps to enable early development
Initiatives
  • 2015 IP Licensing Survey
    IP Licensing involves many parameters: Royalty, Indemnity, Maintenance & Support, Liability, Modification Rights, etc.  Participants in this short survey will receive free access to the follow-on report.  All data will be kept confidential (i.e., participants will not be mentioned by name or company name).
  • Licensing Executives Society (LES) – Work together to understand, promote, and implement IP licensing best practices for the semiconductor industry.

Contact Information

Harrison Beasley
Director, Technology
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Warren Savage, CEO, IPextreme

Meeting Schedule

What's New in this Group?

Intellectual Property

Q4 2014 Meeting

Date: October 22, 2015
Time: 9:00 a.m. – Noon
Location: Synopsys, Mountain View, CA

Q1 2016 Meeting

Date: January 21, 2016
Time: 9:00 a.m. – Noon
Location: Rambus, Mountain View, CA

Q2 2016 Meeting

Date: April TBD, 2016
Time: 9:00 a.m. – Noon
Location: Synopsys, Mountain View, CA

Q3 2015 Meeting

Date: July 21, 2016
Time: 9:00 a.m. – Noon
Location: Rambus, Mountain View, CA

Presentations

What's New in this Group?

Jul 16, 2015

Apr 16, 2015

Jan 22, 2015

Oct 23, 2014

Jul 24, 2014

Apr 9, 2014

Jan 23, 2014

Oct 17, 2013

Jul 18, 2013

Apr 17, 2013

Jan 23, 2013

Nov 7, 2012

Oct 23, 2012

Sept 25, 2012

Aug 7, 2012

Mar 1, 2012

Minutes

What's New in this Group?
2015 Meeting Minutes
  • APR 16, 2015 Video from IP Integration Panel and IP for Custom Analog Presentation
  • JAN 22, 2015 Video from IP Business Model and IP Management Panels
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes

Tools

What's New in this Group?
Intellectual Property Source Selection

The IP working group is actively exploring intellectual property source selection decisions.  We have completed both generic and SerDes specific version of this valuable tool.

This downloadable Excel workbook guides the user in evaluative potential sources of Intellectual Property block for Risk, Cost, and Performance.

The team will continue to generate version specific to individual IP block.  Your contribution, analysis and questions are welcomed.

IP Source Selection Tool

IP Source Selection Tool – SerDes

IP ROI Calculator

The IP ROI Calculator was created to provide a framework that allows users to add their own data and criteria for their Make vs. Buy decision. Functioning as an excel workbook, the calculator has five main sections:

  • Introduction
  • IP Qualitative
  • IP Make vs. Buy
  • Product ROI
  • Sensitivity Analysis

Read more about the IP ROI Calculator.

Licensing Executives Society (LES) 

Semiconductor Committee Mission:

  • Provide a forum for education, discussion and networking for all interested LES members concerning the technology transfer and licensing of semiconductor technology, patents, and products.
  • Identify important issues in semiconductor licensing and facilitate member engagement to discuss and address these issues.
  • Disseminate the results of the group’s work within LES via publications and workshop sessions at LES meetings or in special seminars

Projects

What's New in this Group?
Intellectual Property Source Selection

The IP working group is actively exploring intellectual property source selection decisions.  We have completed both generic and SerDes specific version of this valuable tool.

This downloadable Excel workbook guides the user in evaluative potential sources of Intellectual Property block for Risk, Cost, and Performance.

The team will continue to generate version specific to individual IP block.  Your contribution, analysis and questions are welcomed.

IP Source Selection Tool

News

What's New in this Group?

MCCI USB Host stack for Win 10 IoT Core on Raspberry Pi - See more at: http://www.electronicsweekly.com/news/design/embedded-systems/mcci-usb-host-stack-win-10-iot-core-raspberry-pi-2015-07/#sthash.9TYqrqCF.dpuf
Wednesday, July 8, 2015
Electronics Weekly
MCCI is providing its TrueTask USB Host stack as the connectivity engine for Windows 10 IoT Core OS targeting Raspberry Pi. A quality USB host stack is needed to make Windows 10 on Raspberry Pi 2 suitable for for IoT development. "Creating USB host stack is risky because of the testing and requirements needed to be compatible with the huge variety of devices," says MCCI CEO Terry Moore., " TrueTask is pre-tested and pre-verified so our customers can focus on enhancing their IoT products and don't have to worry about USB connectivity." - See more at: http://www.electronicsweekly.com/news/design/embedded-systems/mcci-usb-host-stack-win-10-iot-core-raspberry-pi-2015-07/#sthash.9TYqrqCF.dpuf

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.

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