Intellectual Property Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • Tools
  • Projects
  • News

Overview

What's New in this Group?

Intellectual Property (IP) is a cornerstone of the semiconductor industry.  Semiconductor companies generate, buy, and sell IP cores as a normal course of business.  Many companies have been purchased based solely on the value of their IP.  Additionally, patent rights are regularly traded between industry companies. However, issues abound with the purchase of IP in terms of understanding the actual IP content, licensing terms, royalty payments, etc..  Similarly, IP sellers strive to provide IP that is viable for a broad user base.

Vision

Provide a forum for open discussion of intellectual property best practices, licensing trends, sourcing / supplying, and process improvements.

Mission

Provide industry education relevant to IP Licensing, IP reuse, IP roadmaps.  Understand IP trends through timely surveys and analysis.

Objectives
  • Periodic IP Licensing best practices survey and analysis
  • Improve IP strategies by applying metrics that align buyers and sellers on key success indicators
  • Identify IP sourcing process advances and provide community education
  • Generate creative ideas to source IP to start-ups, envision IP as a product, and provide guidance on IP roadmaps to enable early development
Initiatives
  • IP Licensing Survey – 2014 GSA IP Licensing survey is OPEN and will close on April 30.  We seek IP representatives from both IP companies and semiconductor companies to complete the survey and add to the overall understanding of the increasingly important IP segment of the semiconductor market.  All participants will receive the results of the survey.
  • Licensing Executives Society (LES) – Work together to understand, promote, and implement IP licensing best practices for the semiconductor industry.

Contact Information

Harrison Beasley
Director, Technology
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Warren Savage, CEO, IPextreme

Meeting Schedule

What's New in this Group?
Q4 2014 Meeting

IP Working Group
Date: October 23, 2014
Time: 9:00 a.m. – Noon
Location: Rambus, Sunnyvale, CA

Overview & Registration

Q1 2015 Meeting

IP Working Group
Date: January 22, 2015
Time: 9:00 a.m. – Noon
Location: Synopsys, Mountain View, CA

Q2 2015 Meeting

IP Working Group
Date: April 15, 2014
Time: 9:00 a.m. – Noon
Location: IPextreme, Campbell, CA

Q3 2015 Meeting

IP Working Group
Date: July 23, 2014
Time: 9:00 a.m. – Noon
Location: Synopsys, Mountain View, CA

Presentations

What's New in this Group?

Jul 24, 2014

Apr 9, 2014

Jan 23, 2014

Oct 17, 2013

Jul 18, 2013

Apr 17, 2013

Jan 23, 2013

Nov 7, 2012

Oct 23, 2012

Sept 25, 2012

Aug 7, 2012

Mar 1, 2012

Minutes

What's New in this Group?
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes

Tools

What's New in this Group?
IP ROI Calculator

The IP ROI Calculator was created to provide a framework that allows users to add their own data and criteria for their Make vs. Buy decision. Functioning as an excel workbook, the calculator has five main sections:

  • Introduction
  • IP Qualitative
  • IP Make vs. Buy
  • Product ROI
  • Sensitivity Analysis

Read more about the IP ROI Calculator.

Licensing Executives Society (LES) 

Semiconductor Committee Mission:

  • Provide a forum for education, discussion and networking for all interested LES members concerning the technology transfer and licensing of semiconductor technology, patents, and products.
  • Identify important issues in semiconductor licensing and facilitate member engagement to discuss and address these issues.
  • Disseminate the results of the group’s work within LES via publications and workshop sessions at LES meetings or in special seminars

Projects

What's New in this Group?
Intellectual Property Source Selection

The IP working group is actively exploring intellectual property source selection decisions.  The draft document below is available for review and comment.

IP Source Selection Tool

News

What's New in this Group?

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.

MEMS treads logic road
Wednesday, August 6, 2014
EETimes Asia
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.

TSMC Details Family of Chip Stacks
Thursday, April 24, 2014
EE Times
TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations. The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.

3D EDA brings together proven 2D solutions
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year. "This is unprecedented," said Kelvin Low, senior director of marketing at Samsung. "It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model," he added. Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

Fast & Accurate Thermal Analysis of 3D-ICs
Monday, April 14, 2014
SemiWiki
As Moore's law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it's extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, Tmax control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.

FinFET Custom Design
Wednesday, April 2, 2014
SemiWiki
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel
Wednesday, March 19, 2014
3D InCites
All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it's clear that we've got some very different opinions regarding one of my pet peeves - the ever-expanding and increasingly complex advanced packaging nomenclature.

Silicon Photonics Bring New Capabilities To IC Design
Tuesday, March 18, 2014

These days, electronic systems and products are always looking for increased communication speed and lower power consumption. Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth. Early applications to short-run data communications in the data center, described by Intel and Cisco among others, are capturing attention in the press. With the world headed toward the Internet of Everything, more capable and efficient server farms are interesting to many.

Plug-and-play test strategy for 3D ICs
Monday, March 17, 2014
Solid State Technology
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield. Yield is typically determined using silicon area as a key factor; the larger the die, the more likely it contains a fabrication defect. One way to improve yield, then, is to segment the large and potentially low-yielding die into multiple smaller die that are individually tested before being placed together in a 3D IC.

Big sell: IP trends and strategies
Tuesday, March 11, 2014
Semiconductor Manufacturing & Design
Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

A Flexible Test Strategy for 3D ICs
Thursday, March 6, 2014
EEJournal
The semiconductor industry is ramping up for the wider adoption of 3D ICs, which promise better performance, reduced power, and improved yield. While some aspects of true 3D ICs are still evolving, solutions for testing 3D ICs are ready today. The test strategy for 3D ICs has two goals: improving the pre-packaged test quality and establishing new tests between the stacked dice. We describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die, stack, and partial stack-level tests to use the same test interface, and to retarget die-level tests directly to the selected die within the 3D stack.

Cost-efficient 3D IC wafer processing without adhesives
Monday, January 27, 2014
EE Times Asia
During a 3D TSV Summit on Minatech' campus in Grenoble, France, a resounding topic across the floor was on how to cut costs in 3D IC packaging. Disregarding IC design, there are many processes involved before dies can be stacked together. These include the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.

HOME

Bookmark the permalink.
True CircuitTSMCSynopsysCortusBristleconeSamsung