- Overview
- Meeting Schedule
- Presentations
- Minutes
- Tools
- News
Overview
Intellectual Property (IP) is a cornerstone of the semiconductor industry. Semiconductor companies generate, buy, and sell IP cores as a normal course of business. Many companies have been purchased based solely on the value of their IP. Additionally, patent rights are regularly traded between industry companies. However, issues abound with the purchase of IP in terms of understanding the actual IP content, licensing terms, royalty payments, etc.. Similarly, IP sellers strive to provide IP that is viable for a broad user base.
Vision
Provide a forum for open discussion of intellectual property best practices, licensing trends, sourcing / supplying, and process improvements.
Mission
Provide industry education relevant to IP Licensing, IP reuse, IP roadmaps. Understand IP trends through timely surveys and analysis.
Objectives
- Periodic IP Licensing best practices survey and analysis
- Improve IP strategies by applying metrics that align buyers and sellers on key success indicators
- Identify IP sourcing process advances and provide community education
- Generate creative ideas to source IP to start-ups, envision IP as a product, and provide guidance on IP roadmaps to enable early development
Initiatives
- IP Licensing Survey – Analyze licensing trends to help reduce negotiation time and cost required to complete licensing agreements.
- IP Blogs - Forum to discuss multiple perspectives on the IP ecosystem.
- Licensing Executives Society (LES) – Work together to understand, promote, and implement IP licensing best practices for the semiconductor industry.
Contact Information
Harrison Beasley
972.489.0248
beasley@gsaglobal.org
Working Group Chair
Warren Savage, CEO, IPextreme
Meeting Schedule
Q3 2013 Meeting
IP Working Group Meeting
Date: July 18, 2013
Time: 9:00 a.m.
Location: Synopsys, Mountain View, CA
Q4 2013 Meeting
IP Working Group Meeting
Date: October 24, 2013
Time: 9:00 a.m.
Location: Silicon Valley
Q1 2014 Meeting
IP Working Group Meeting
Date: January, 2014
Time: 9:00 a.m.
Location: TBD
Speakers: TBD
Q2 2014 Meeting
IP Working Group Meeting
Date: April, 2014
Time: 9:00 a.m.
Location: TBD
Presentations
| Date: | April 17, 2013 |
| Location: | IPextreme, Campbell, CA |
| Meeting: | IP Working Group Meeting |
| Presentations: | Licensing Executive Society (PDF, 1,989 KB) Steffan Tamme, Rambus Managing the IP Sourcing Process (PDF, 557 KB) Philippe Quinio, STMicro |
| Date: | January 23, 2013 |
| Location: | Synopsys, Mountain View, CA |
| Meeting: | IP Working Group Meeting |
| Presentations: | IP WG Overview (PDF, 722 KB) Harrison Beasley, GSA Maximizing the Value of Your Internal IP (PDF, 896 KB) Warren Savage, IPextreme Presentation Video Link Designing with FinFETs Evolution or Revolution (PDF, 1,442 KB) Jamil Kawa, Synopsys |
| Date: | November 7, 2012 |
| Location: | Cavium, San Jose, CA |
| Meeting: | Technology Steering Committee – Working Group Review |
| Presentations: | IP Working Group Update (PDF, 722 KB) Warren Savage, IPextreme |
| Date: | October 23, 2012 |
| Location: | Atrenta, San Jose, CA |
| Meeting: | IP Working Group Meeting |
| Presentations: | IP Working Group Overview (PDF, 456 KB) Harrison Beasley, GSA A Systematic Approach to Soft IP Quality (PDF, 1,223 KB) Anuj Kumar, Atrenta Licensing the Crown Jewels (PDF, 1,288 KB) Kevin Klein, Freescale |
| Date: | September 25, 2012 |
| Location: | Mentor Graphics, Fremont, CA |
| Meeting: | IP Roundtable |
| Presentations: | IP Roundtable Overview (PDF 780 KB) Warren Savage, Chief Executive Officer, IPextreme |
| Date: | August 7, 2012 |
| Location: | Teleconference & Web Cast |
| Meeting: | IP Working Group |
| Presentations: | IP WG Agenda Warren Savage, Chief Executive Officer, IPextreme Mobile Socs – Longer Battery Life Jack Browne, SR. VP Sales & Marketing, Sonics, Inc TSMC9000 IP Quality Dan Kochpatcharin, Deputy Director IP Portfolio Marketing, TSMC |
| Date: | March 1, 2012 |
| Location: | Austin, TX |
| Meeting: | GSA IP Summit |
| Presentations: | Introduction to IP Working Group Warren Savage, Chief Executive Officer, IPextreme Keynote: Make vs. Buy Mark Downing, Vice President of Corporate Strategy & Business Development, Silicon Laboratories Keynote: Licensing the Crown Jewels – Capitalizing the Full Assets of Your Company Kevin Klein, Director of IP Licensing, Freescale Semiconductor Panel Discussion: What Keeps You Up at Night? Moderator: Warren Savage, Chief Executive Officer, IPextreme |
Minutes
2013 Meeting Minutes
- APR 17, 2013 Working Group Minutes (PDF, 764 KB)
- MAR 14, 2013 Core Team Minutes (PDF, 753 KB)
- JAN 23, 2013 Working Group Minutes (PDF, 763 KB)
2012 Meeting Minutes
- NOV 27, 2012 Core Team Minutes (PDF, 753 KB)
- OCT 23, 2012 Working Group Minutes (PDF, 760 KB)
- SEP 25, 2012 Roundtable Minutes (PDF, 777 KB)
- SEP 4, 2012 Core Team Minutes (PDF, 785 KB)
- AUG 7, 2012 Working Group Minutes (PDF, 785 KB)
- JUN 12, 2012 Working Group Minutes (PDF, 38 KB)
- MAY 15, 2012 Working Group Minutes (PDF, 40 KB)
- APR 3, 2012 Working Group Minutes (PDF, 26 KB)
- JAN 10, 2012 Working Group Minutes (PDF, 33 KB)
Tools
IP ROI Calculator
The IP ROI Calculator was created to provide a framework that allows users to add their own data and criteria for their Make vs. Buy decision. Functioning as an excel workbook, the calculator has five main sections:
- Introduction
- IP Qualitative
- IP Make vs. Buy
- Product ROI
- Sensitivity Analysis
Read more about the IP ROI Calculator.
Licensing Executives Society (LES)
Semiconductor Committee Mission:
- Provide a forum for education, discussion and networking for all interested LES members concerning the technology transfer and licensing of semiconductor technology, patents, and products.
- Identify important issues in semiconductor licensing and facilitate member engagement to discuss and address these issues.
- Disseminate the results of the group’s work within LES via publications and workshop sessions at LES meetings or in special seminars
News
Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs
Monday, May 20, 2013
3D InCites
WILSONVILLE, Ore., May 20, 2013Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzarons 3D IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.
3D Brings Test Into Fashion
Friday, May 17, 2013
Semiconductor Manufacturing
As integral and critical as test is to the success of an SoC, it isnt always one of those topics in semiconductor design that seems fashionable.
But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, [Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. Youre on autopilot until you hit a disruption, and 3D represents a disruption.
MOSIS joins push for silicon photonics tech
Monday, May 6, 2013
EE Times Asia
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has partnered with ePIXfab, the European Silicon Photonics support centre that offers low-cost prototyping services for photonic ICs. According to the company, the venture gives MOSIS' customers access to Imec's modern fully integrated silicon photonics processes and Tyndall's advanced silicon photonics packaging technology.
Adaptive IP is the wave of the future
Thursday, May 2, 2013
EE Times
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future.
More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.
Semiconductor PLM Needs to be smart for techies
Thursday, April 18, 2013
SemiWiki
During my long career in semiconductor, EDA, I have heard, believed and experienced that this is a knowledge industry swamped with rapid innovation and technology drivers; typical manufacturing product development processes like Gantt charts and others do not apply here. The fallback is that most of the time estimations are ad hoc, based on gut-feel or expert opinion. Not only schedule, most of the processes are run by individual preferences; in other words the whole process is more people driven than process driven. Naturally, we see missed targets, re-spins, cost overruns, lost market opportunities and so on. It is said that success rate to first silicon is 0%! And we attribute the Product Lifecycle Management (PLM) issues to high complexity of designs at nanometer scale, high density, analog and digital mixed-signal and so on.
Cavendish Kinetics MEMS Gets Actual Mbps Nearer To Theoretical Mbps
Wednesday, April 17, 2013
Electronics Weekly
Cavendish Kinetics has an answer to the the widening gap between actual mobile data rates and theoretically achievable data rates.
GSM in the 90s achieved actual data rates close to the theoretical maxiimum but, ever since, the gap between actual and theoretical has widened.
'4G technology supports data rates of 80Mbps,' says Cavendish Kinetics, 'but in practice delivers only 1-8Mbps for many users.'
Going 3D by Evolution Rather Than Revolution: 2.5D, 3D, 5.5D-IC and Beyond
Friday, April 12, 2013
Synopsys
Introduction
In 2004, a visionary keynote by STMicroelectronics Carlo Cognetti at the Napa KGD Packaging & Test Workshop entitled Much More than Moore proposed that more than Moore (i.e., the 3D-IC integration of complete, heterogeneous systems in the same package) is complementary to silicon-level integration, which is ruled by the well-known and established more of Moore, and suggested that the final result of combining more than Moore and more of Moore is surprisingly more advanced than what is allowed by the simple progression of the technology nodes.
At that time, the road to 3D-IC integration was unclear, R&D engineers at all levels of the supply chain were debating the different options, and 3D-IC was considered a technology of the future. We have made a great deal of progress, and today, 3D-IC integration has become the technology for the future rather than the technology of the future.
TSMC Responds to Samsung!
Friday, April 12, 2013
SemiWiki
This was the 19th annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.
Health consciousness fuels quadruple growth for MEMS sensors
Thursday, April 11, 2013
EE Times
Activity monitors such as the FitLinxx Pebble and Fitbug, for instance, are increasingly finding their way into consumers' hands as employers seek to augment their corporate wellness strategies, noted Shane Walker, senior manager for consumer & digital health research at IHS. "In the United States, this is due in part to the growth of consumer-directed healthcare plans and the Affordable Care Act, which is incentivizing insurers. These corporate programmes are opening yet another channel of distribution for new monitoring devices," he said.
TSMC on Collaboration: JIT Ecosystem Development
Wednesday, March 27, 2013
SemiWiki
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.
Want 10nm Wafers? That'll Cost You
Sunday, February 10, 2013
SemiWiki
As you know, I've been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones's "fireside chat".
20nm IP Portability Appears Virtually Impossible
Monday, February 4, 2013
System level Design
Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs.
European 3D TSV Summit: Focus on Cost of Ownership
Thursday, January 31, 2013
3D InCites
Now that the technology bricks for building 2.5D devices and 3D ICs have been essentially qualified, the focus has turned to optimizing them for improved cost of ownership (CoO). At last weeks European 3D TSV Summit, in Grenoble, France, many of the supplier presentations demonstrated how their companies have been working to optimize qualified 3D TSV technologies across the process flow.
In Search of MEMS Standards
Monday, January 28, 2013
EE Journal
MEMS is in need of standards.
Ive heard that declaration many times over the last few months. But just try to search the Internet for evidence of standards or even standardization efforts, and youll find
stuff, but you have to look hard and follow many fruitless threads to get there, and its anything but conclusive. Discussions with the actual people involved paint a very different picture from that which emerges from the Internet.
Qualcomm joins IMEC core CMOS R&D program
Monday, January 28, 2013
EE Times
Qualcomm Technology Inc. is has joined the core CMOS R&D collaborative research program of nanoelectronics research institute IMEC (Leuven, Belgium), the institute said.
Qualcomm Technology, a wholly-owned subsidiary of Qualcomm Inc. (San Diego, Calif.), joins leading chip companies that included, as of July 2012: Elpida, Fujitsu, Globalfoundries, Intel, Micron, Panasonic, Samsung, Taiwan Semiconductor Manufacturing Co., SK Hynix, Toshiba/Sandisk, and Sony
RTI 3D ASIP Part 1
Monday, January 28, 2013
Solid State Technology
Every year since 2005 the 3DIC season as ended with the Research Triangle Institute-sponsored Architectures for Semiconductor Integration and Packaging Conference (which I coined ASIP several years ago as I became tired of typing out the whole phrase). This conference -- with its totally invited agenda -- gives us a good chance to look back at what has happened during the year.
Synopsys boosts uptake of FinFETs
Friday, January 25, 2013
http://www.eetasia.com/ART_8800681027_480100_NT_c7bebfc6.HTM
Synopsys Inc. has revealed what it says is a comprehensive solution for FinFET-based semiconductor designs that includes various DesignWare Embedded Memory and Logic Library IP, silicon-proven design tools from the Galaxy Implementation Platform, and foundry-endorsed extraction, simulation and modelling tools. It also includes TCAD and mask synthesis products used by foundries for FinFET process development, added the firm.
Mentor @ the TSMC Open Innovation Platform Forum
Wednesday, January 16, 2013
SemiWiki
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.
Texas fab licenses bonding for 3-D ICs
Wednesday, January 16, 2013
EE Times
LONDON Specialty foundry Novati Technologies Inc. has licensed a family of direct oxide bonding technique froms Ziptronix Inc. (Morrisville, North Carolina) for use in the assembly of 3-D components.
2013 Predictions for 3D ICs as told by Everyone - Part 2
Tuesday, January 15, 2013
3D InCites
No sooner did I post last weeks curation of predictions for the semiconductor industry, and particularly for 3D ICs, than several more popped up online. I suspect this type of thing to continue for the next few weeks, and I will try and continue to cherry-pick the ones that made reference to 3D integration.
Why USB 3.0 Will Drive SoC Verification in 2013
Tuesday, January 15, 2013
Chip Estimate
We might not realize it yet, but 2012 will be remembered in tech circles as the year that USB changed the face of electronics. Much was written last year about big-picture issues facing the electronics industry, like the conflicting strategies of Apple vs. Samsung and ARM vs. Intel, but little has been written about developments quietly taking place in the USB ecosystem that will set the course for future consumer electronics systems. These USB developments are impacting both personal computing and mobile devices and are opening a host of new product opportunities. But they are also increasing demands on design and verification teams, and increasing the need for products that assist in pre-silicon functional verification, particularly verification IP (VIP).
IBM tops patent list, Asian firms dominate
Monday, January 14, 2013
EE Times Asia
The U.S. patent office issued 253,155 utility patents in 2012, the highest annual number on record and an increase of about 13 per cent over 2011, IFI Claims estimates.
For the twentieth year in a row, IBM was at the top of the list, receiving 6,478 utility patents in 2012, up nearly 5 per cent from 2011. Inventions focused on key areas such as Big Data, analytics, mobile, software-defined environments and cognitive systems. Rounding up the top ten are Samsung, Canon, Sony, Panasonic, Microsoft, Toshiba, Hon Hai Precision Industry, General Electric and LG Electronics.
Key intellectual property trends for 2013
Monday, January 14, 2013
EE Times Asia
2012 was the year of intellectual property and patents, with lawsuits, sales and competitive gamesmanships resulting in an increased number of firms actively utilising intellectual assets as viable tools for building their businesses. The likes of Google, Samsung, Kodak, Apple and Marvell were linked to millions of dollars in litigation.
Hogan says retooling underway for custom 2.0
Friday, January 11, 2013
EE Times
The Custom 1.0 era began around 1980 and has had a run for over three decades. The early SPICE engines were mostly close cousins with UC Berkeley SPICE and ran on mainframes. Cadence Analog Artist was the first successful commercial solution for Custom 1.0, tying schematics to simulation and annotating simulation results to the schematic. Analog Artist has evolved to become Cadence Analog Design Environment (ADE) and still dominates the market today.
Predictions for 2013 EDA/IP
Thursday, January 10, 2013
EE Times
A few weeks ago, I asked many people in the industry for their predictions for 2013. I separately asked for those related to technology in general, to the EDA industry and for business predictions. In the first part I covered technology predictions. Today, we look at those related to EDA and the IP industry, and as can be expected most follow the party line fairly closely.
