MEMS Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • News


What's New in this Group?

The MEMS industry has seen tremendous advancements in recent years and is one of the fastest growing segments in the semiconductor product industry.  In order to keep this pace, new applications and market segments have to be continuously identified.  In addition, with the downward price pressure and shorter time-to-market needs brought on by the consumer, efficiencies in design, manufacturing, integration, software development and related processes need to be realized. The MEMS Working Group was formed to address these challenges on an industry-wide scale.


To provide a neutral forum where members can exchange ideas, stimulate thought, and collaborate on solutions to have a positive impact on the growth and profitability of the MEMS industry.


To bring together leading representatives from the MEMS industry and semiconductor design to (1) collaborate on solutions that improve the technical and economic landscape in design and manufacturing, and  (2) discuss commercial requirements for new applications, market segments and growth areas  to address the cost down and time-to-market demands of the end customer.

  • Continually identify and explore key application areas that are expected to drive the growth of the MEMS industry over a rolling five year period
  • Identify and promote areas of collaboration for integration of MEMS into multi-disciplinary systems
  • Help identify economies of reuse through homogenization of design and manufacturing resources (versus a “one product, one process, one package” mentality)
  • Help identify other areas of improvement in design, manufacturing or processes that help to reduce product costs and accelerate time to market

Contact Information

Harrison Beasley
Director, Technology

Working Group Chair
Maarten Vranes, MEMS Journal

Meeting Schedule

What's New in this Group?
Q4 2014 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: December 10, 2014
Time: 2:00 p.m. – 5:00 p.m.
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Q1 2015 Meeting

MEMS Working Group Meeting
Host: TBD
Date: March 18, 2015
Time: 2:00  – 5:00 p.m.
Location: Silicon Valley

Q2 2015 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: June 17, 2015
Time: 2:00 – 5:00 p.m.
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Q3 2013 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: September TBD, 2015
Time: 2:00 – 5:00 p.m.
Location: 3165 Kifer Rd, Bldg B, San Jose, CA


What's New in this Group?

Jun 18, 2014

Mar 26, 2014

Sep 25, 2013

Jun 12, 2013

Mar 20, 2013

Dec 12, 2012

Nov 7, 2012

Sept 26, 2012

Jun 18, 2012


What's New in this Group?
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes


What's New in this Group?

MEMS treads logic road
Wednesday, August 6, 2014
EETimes Asia
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.

TSMC Details Family of Chip Stacks
Thursday, April 24, 2014
EE Times
TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations. The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.

3D EDA brings together proven 2D solutions
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year. "This is unprecedented," said Kelvin Low, senior director of marketing at Samsung. "It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model," he added. Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

Fast & Accurate Thermal Analysis of 3D-ICs
Monday, April 14, 2014
As Moore's law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it's extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, Tmax control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.

FinFET Custom Design
Wednesday, April 2, 2014
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel
Wednesday, March 19, 2014
3D InCites
All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it's clear that we've got some very different opinions regarding one of my pet peeves - the ever-expanding and increasingly complex advanced packaging nomenclature.

Silicon Photonics Bring New Capabilities To IC Design
Tuesday, March 18, 2014

These days, electronic systems and products are always looking for increased communication speed and lower power consumption. Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth. Early applications to short-run data communications in the data center, described by Intel and Cisco among others, are capturing attention in the press. With the world headed toward the Internet of Everything, more capable and efficient server farms are interesting to many.

Plug-and-play test strategy for 3D ICs
Monday, March 17, 2014
Solid State Technology
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield. Yield is typically determined using silicon area as a key factor; the larger the die, the more likely it contains a fabrication defect. One way to improve yield, then, is to segment the large and potentially low-yielding die into multiple smaller die that are individually tested before being placed together in a 3D IC.

Big sell: IP trends and strategies
Tuesday, March 11, 2014
Semiconductor Manufacturing & Design
Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

Cost-efficient 3D IC wafer processing without adhesives
Monday, January 27, 2014
EE Times Asia
During a 3D TSV Summit on Minatech' campus in Grenoble, France, a resounding topic across the floor was on how to cut costs in 3D IC packaging. Disregarding IC design, there are many processes involved before dies can be stacked together. These include the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.

China's SMIC Responds to Soaring 3D IC Market
Monday, October 21, 2013
EE Times
In hopes of getting a piece of action in the rapidly growing thru-silicon-via technology-based 2.5D and 3D IC market, China's leading foundry, Semiconductor Manufacturing International Corp. (SMIC), announced Monday that it has formed an R&D and manufacturing center dedicated to vision, sensors, and 3D IC.

Xilinx, TSMC reach volume production on 28nm 3D ICs
Monday, October 21, 2013
Xilinx and TSMC have jointly announced production release of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous 3D ICs in production. With this milestone, all Xilinx 28nm 3D IC families are now in volume production. These 28nm devices were developed on TSMC's chip-on-wafer-on-substrate (CoWoS) 3D IC process that produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device, the companies said.

TU Delft, Imec co-author test flow for 3D IC optimisation
Friday, October 11, 2013
EE Times Asia
The Delft University of Technology and Imec recently co-developed a new test flow cost modelling tool for 2.5 and 3D stacked integrated circuits. 3D-COSTAR aims to optimise the test flow of 3D stacked ICs by compiling the yields and costs of design, manufacturing packaging and logistics.


Bookmark the permalink.
SamsungUMCAmkor TechnologyTrue CircuitOptimal+TSMCeSilicon