MEMS Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • Projects
  • News

Overview

What's New in this Group?

The MEMS industry has seen tremendous advancements in recent years and is one of the fastest growing segments in the semiconductor product industry.  In order to keep this pace, new applications and market segments have to be continuously identified.  In addition, with the downward price pressure and shorter time-to-market needs brought on by the consumer, efficiencies in design, manufacturing, integration, software development and related processes need to be realized. The MEMS Working Group was formed to address these challenges on an industry-wide scale.

Vision

To provide a neutral forum where members can exchange ideas, stimulate thought, and collaborate on solutions to have a positive impact on the growth and profitability of the MEMS industry.

Mission

To bring together leading representatives from the MEMS industry and semiconductor design to (1) collaborate on solutions that improve the technical and economic landscape in design and manufacturing, and  (2) discuss commercial requirements for new applications, market segments and growth areas  to address the cost down and time-to-market demands of the end customer.

Objectives
  • Continually identify and explore key application areas that are expected to drive the growth of the MEMS industry over a rolling five year period
  • Identify and promote areas of collaboration for integration of MEMS into multi-disciplinary systems
  • Help identify economies of reuse through homogenization of design and manufacturing resources (versus a “one product, one process, one package” mentality)
  • Help identify other areas of improvement in design, manufacturing or processes that help to reduce product costs and accelerate time to market

Contact Information

Harrison Beasley
Director, Technology
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Maarten Vranes, MEMS Journal

Meeting Schedule

What's New in this Group?

MEMS Technical Congress – May 6-7 in Boston, MA

Q2 2015 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: June 18, 2015
Time: 9:30 am  – Noon
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Q3 2015 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: September 23, 2015
Time: 9:30 am  – Noon
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Q4 2015 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: December 12, 2015
Time: 9:30 am  – Noon
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Q1 2016 Meeting

MEMS Working Group Meeting
Host: Qualcomm
Date: March TBD, 2016
Time: 9:30 am  – Noon
Location: 3165 Kifer Rd, Bldg B, San Jose, CA

Presentations

What's New in this Group?

March 26, 2015

Dec 10, 2014

Sep 9, 2014

Jun 18, 2014

Mar 26, 2014

Sep 25, 2013

Jun 12, 2013

Mar 20, 2013

Dec 12, 2012

Nov 7, 2012

Sept 26, 2012

Jun 18, 2012

Minutes

What's New in this Group?
2014 Meeting Minutes
2013 Meeting Minutes
2012 Meeting Minutes

Projects

MEMS Projects Page

News

What's New in this Group?

PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
3D InCites
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.

MEMS treads logic road
Wednesday, August 6, 2014
EETimes Asia
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.

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