- Meeting Schedule
In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. In April 2010, the MOS-AK/GSA Modeling Working Group then merged its efforts with GSA’s MS/RF Model Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK’s purpose, initiatives and deliverables as outlined below.
To play a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.
- Encourage interaction and sharing of all information related to compact modeling at all levels of the device and circuit characterization, modeling and simulations. The Group aspires to build a community with global connections by:
- Promoting standardization of compact models and its implementation into software tools
- Connecting national and local modeling groups
- Building strong bilateral ties with similar organizations around the world
- Conduct regular meetings with industry players and academia to exchange information on the strengths and weaknesses of the industrialization of compact models. Activities include:
- Drafting of standards and providing a center of competence for engineers, designers, managers and decision makers
- Evaluating worldwide best practices and success stories
- Delivering a comprehensive view of compact modeling education
- The Group believes that the transfer of advanced compact modeling methodologies to the industry can be accelerated by providing comprehensive reports and reference papers on the subjects of:
- Basic issues and concepts of device characterization and compact modeling
- Global device characterization and compact modeling issues
- Examples and analysis of best practice of the commercialization of compact models
North America: Pekka Ojala, Exar Corporation
South America: Prof. Gilson I Wirth, Universidade Federal Do Rio Grande Do Sul (UFRGS), Brazil
Europe: Ehrenfried Seebacher, austriamicrosystems AG
Asia: Goichi Yokomizo, STARC
Q1 2014 Meeting
MOS-AK / GSA Modeling
Date: April TBD
Location: London (UK)
FinFET Custom Design
Wednesday, April 2, 2014
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.
UTBB FDSOI Devices Featuring 20nm Gate Length
Friday, January 10, 2014
Did you go to IEDM 2013 in Washington DC ? You may have attended to the "Advanced CMOS Technology Platform" chaired by TSMC, and listen to the FD-SOI related presentation "High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond". According with the abstract, this paper is the first time report of "high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET)." If you didn't go to Washington DC, or not familiar with FD-SOI, having a look at FD-SOI device architecture could help:
China's SMIC Responds to Soaring 3D IC Market
Monday, October 21, 2013
In hopes of getting a piece of action in the rapidly growing thru-silicon-via technology-based 2.5D and 3D IC market, China's leading foundry, Semiconductor Manufacturing International Corp. (SMIC), announced Monday that it has formed an R&D and manufacturing center dedicated to vision, sensors, and 3D IC.
Adaptive IP is the wave of the future
Thursday, May 2, 2013
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future. More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.
MOS-AK/GSA Munich Workshop Press Note
Monday, April 29, 2013
The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, completed its annual spring compact modeling workshop on April 11-12, 2013 at the Institute for Technical Electronics, TUM, Munich. The event received full sponsorship from leading industrial partners including MunEDA and Tanner EDA. The German Branch of IEEE EDS was the workshop technical program promoter. More than 30 international academic researchers and modeling engineers attended three sessions to hear 12 technical compact modeling presentations.