MOS-AK / GSA Modeling Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • News

Overview

In January 2009, GSA merged its  efforts with MOS-AK,  a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. In April 2010, the  MOS-AK/GSA Modeling Working Group then merged its efforts with GSA’s MS/RF Model Working Group. Its purpose, initiatives and  deliverables coincide with  MOS-AK’s purpose, initiatives and deliverables as outlined below.

Mission

To play a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.

Objectives

To Connect:

  • Encourage interaction and sharing of all information related to compact modeling at all levels of the device and circuit characterization, modeling and simulations. The Group aspires to build a community with global connections by:
    • Promoting standardization of compact models and its implementation into software tools
    • Connecting national and local modeling groups
    • Building strong bilateral ties with similar organizations around the world

To Benchmark:

  • Conduct regular meetings with industry players and academia to exchange information on the strengths and weaknesses of the industrialization of compact models. Activities include:
    • Drafting of standards and providing a center of competence for engineers, designers, managers and decision makers
    • Evaluating worldwide best practices and success stories
    • Delivering a comprehensive view of compact modeling education

To Educate:

  • The Group believes that the transfer of advanced compact modeling methodologies to the industry can be accelerated by providing comprehensive reports and reference papers on the subjects of:
    • Basic issues and concepts of device characterization and compact modeling
    • Global device characterization and compact modeling issues
    • Examples and analysis of best practice of the commercialization of compact models
Contact  Information:

MOS-AK/GSA Group Manager
Wladek Grabinski
wladek@mos-ak.org
Harrison Beasley, GSA
hbeasley@gsaglobal.org

North America: Pekka Ojala, Exar Corporation
South America: Prof. Gilson I Wirth, Universidade Federal Do Rio Grande Do Sul (UFRGS),  Brazil
Europe: Ehrenfried Seebacher, austriamicrosystems AG
Asia: Goichi Yokomizo, STARC

Meeting Schedule

Q4 2014 Meeting

MOS-AK / GSA Modeling
Date: December 12
UC Berkeley

Q1 2015 Meeting

MOS-AK / GSA Modeling
Date: Spring 2015
Grenoble, France

MOS/AK – GSA Compact Modeling Website

News

What's New in this Group?

PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
3D InCites
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

FinFET Custom Design
Wednesday, April 2, 2014
SemiWiki
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.

UTBB FDSOI Devices Featuring 20nm Gate Length
Friday, January 10, 2014
SemiWiki
Did you go to IEDM 2013 in Washington DC ? You may have attended to the "Advanced CMOS Technology Platform" chaired by TSMC, and listen to the FD-SOI related presentation "High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond". According with the abstract, this paper is the first time report of "high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET)." If you didn't go to Washington DC, or not familiar with FD-SOI, having a look at FD-SOI device architecture could help:

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