MOS-AK / GSA Modeling Working Group

Overview

In January 2009, GSA merged its  efforts with MOS-AK,  a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. In April 2010, the  MOS-AK/GSA Modeling Working Group then merged its efforts with GSA’s MS/RF Model Working Group. Its purpose, initiatives and  deliverables coincide with  MOS-AK’s purpose, initiatives and deliverables as outlined below.

Mission

To play a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.

Objectives

To Connect:

• Encourage interaction and sharing of all information related to compact modeling at all levels of the device and circuit characterization, modeling and simulations. The Group aspires to build a community with global connections by:
  • Promoting standardization of compact models and its implementation into software tools
  • Connecting national and local modeling groups
  • Building strong bilateral ties with similar organizations around the world

To Benchmark:

• Conduct regular meetings with industry players and academia to exchange information on the strengths and weaknesses of the industrialization of compact models. Activities include:
  • Drafting of standards and providing a center of competence for engineers, designers, managers and decision makers
  • Evaluating worldwide best practices and success stories
  • Delivering a comprehensive view of compact modeling education

To Educate:

• The Group believes that the transfer of advanced compact modeling methodologies to the industry can be accelerated by providing comprehensive reports and reference papers on the subjects of:
  • Basic issues and concepts of device characterization and compact modeling
  • Global device characterization and compact modeling issues
  • Examples and analysis of best practice of the commercialization of compact models

Participants

Those who deal with modeling-related issues, such as model generation, extraction, validation and comparison (modeling engineers, model developers, compact model  designers, etc.).

Meetings

Workshops are held every quarter in either North America, South America, Europe or Asia.

Leadership

North America

Chair: Pekka Ojala, Exar Corporation
O 510.668.7543
E pekka.ojala@exar.com
Co-Chair: Geoffrey Coram, Analog Devices, Inc.
Co-Chair: Jamal Deen, McMaster University
Co-Chair: Roberto Tinti, Agilent EEsof Division

South America

Chair: Prof. Gilson I Wirth, Universidade Federal Do Rio Grande Do Sul (UFRGS),  Brazil
O + 55 (51) 3308-4443
E wirth@inf.ufrgs.br
Co-Chair: Prof. Carlos Galup-Montoro, Universidade Federal de Santa Catarina  (UFSC), Brazil
Co-Chair: Sergio Bampi, Universidade Federal Do Rio Grande Do Sul (UFRGS),  Brazil
Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav – IPN

Europe

Chair: Ehrenfried Seebacher, austriamicrosystems AG
O +43 3136 500 5487
E ehrenfried.seebacher@austriamicrosystems.com
Co-Chair: Alexander Petr, X-FAB Semiconductor Foundries AG
Co-Chair: Benjamin Iniguez, Universitat Rovira I Virgili (URV)
Co-Chair: James Victory, Sentinel IC Technologies

Asia

Chair: Goichi Yokomizo, STARC
O +81-45-478-3750
E yokomizo.goichi@starc.or.jp
Co-Chair: Sadayuki Yoshitomi, Toshiba
Co-Chair: Prof. Xing Zhou, Nanyang Technological University
Co-Chair: A.B. Bhattacharyya, JIIT

MOS-AK/GSA Group Manager

Wladek Grabinski
O +41 22 349 0939
E wladek@mos-ak.org

Contact  Information:

Harrison Beasley
GSA Working Groups Manager
O 972.866.7579 x104
M 972.489.0248
E hbeasley@gsaglobal.org

Meeting Schedule

Q3 2013 Meeting

MOS-AK / GSA Modeling
Date: Sept 20, 2013
Time: 8 a.m.
Location: Marriott Grand, Bucharest, RO
Click here for meeting details

Presentations

Presentations from 2012 / 2013 MOS-AK / GSA Modeling Working Group can be found here

Papers

Additional papers and MOS-AK information can be found here

Verilog-A Compact Model Coding Whitepaper (PDF)
This paper presents recommendations for developers of Verilog-A compact models who want to optimize their models for SPICE-like simulators and to facilitate the integration of said models into different simulators.

News

Adaptive IP is the wave of the future
Thursday, May 2, 2013
EE Times
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future. More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.

MOS-AK/GSA Munich Workshop Press Note
Monday, April 29, 2013
GSA News
The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, completed its annual spring compact modeling workshop on April 11-12, 2013 at the Institute for Technical Electronics, TUM, Munich. The event received full sponsorship from leading industrial partners including MunEDA and Tanner EDA. The German Branch of IEEE EDS was the workshop technical program promoter. More than 30 international academic researchers and modeling engineers attended three sessions to hear 12 technical compact modeling presentations.

TSMC Responds to Samsung!
Friday, April 12, 2013
SemiWiki
This was the 19th annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.

TSMC on Collaboration: JIT Ecosystem Development
Wednesday, March 27, 2013
SemiWiki
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

A Brief History of the Foundry Industry, part 2
Wednesday, March 13, 2013
SemiWiki
Part 1 here. The line between fabless semiconductor companies and IDMs has blurred over the last decade. Back in the 1990s, most IDMs manufactured most of their own product, perhaps using a foundry for a small percentage of additional capacity when required. But their own manufacturing was competitive, both in terms of the capacity of fab they could afford to build, and in terms of process technology.

Assertion Synthesis: Atrenta, Cadence and AMD Tell All
Monday, February 11, 2013
SemiWiki
Assertion Synthesis is a new tool for verification and design engineers that can be used with simulation or emulation. At DVCon Yuan Lu of Atrenta is presenting a tutorial on Atrenta's BugScope along with John Henri Jr of Cadence explaining how it helps emulation and Baosheng Wang of AMD discussing their experiences of the product.

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