Supply Chain Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • News
  • Tools
  • Conflict Minerals

Overview

What's New in this Group?

An efficient and effective semiconductor supply chain addresses every aspect of wafer fabrication, die assembly and test, and product delivery.  The supply chain performs Capacity versus Demand analysis; Capacity Trending, and other issues that could impact successful flow of product.  With the rapid rise of decreased cycle times due to quickly changing consumer markets, the supply chain is under new stresses to ensure a steady supply flow.

Vision

Analyze wafer and assembly pricing trends.   Address supply chain impacts and risks due rapidly changing development needs.  Provide an efficient response capability to statutory regulations.

Mission

Provide an open forum where supply chain executives openly discuss risks and impact due to semiconductor industry consolidation, single point failures, advanced packaging initiatives, and other areas of supply chain management.

Objectives
  • Quarterly wafer and assembly pricing trend analysis
  • Generate reports to address the changing landscape of semiconductor supply chain management
  • Risk assessment and mitigation techniques
  • Best practices sharing
  • Provides information and guidance for Conflict Minerals and other statutory regulations
Initiatives

Wafer Fabrication & Assembly Pricing Survey/Report – The Wafer Fabrication & Assembly Pricing Survey queries fabless companies and IDMs on pricing trends for outsourced wafers and assembly services.  The report includes a written analysis of results and  an interactive online database that allows tailored analysis of wafer pricing, mask set pricing, and assembly pricing.

Contact Information

Harrison Beasley
Director, Techlogy
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Dan Wark, Vice President, Supply Chain Management, Exar Corporation

Meeting Schedule

What's New in this Group?
Q1 2015 Meeting

Supply Chain Working Group
Date: February 19, 2015
Time: 9:00 a.m. – 12:00 p.m.
Location: Elementum, Mountain View, CA

Q2 2015 Meeting

Supply Chain Working Group
Date: May 21, 2015
Time: 9:00 a.m. – 12:00 p.m.
Location: Exar, Fremont, CA

Q3 2015 Meeting

Supply Chain Working Group
Date: August 19, 2015
Time: 9:00 a.m. – 12:00 p.m.
Location: Exar, Fremont, CA

Q4 2015 Meeting

Supply Chain Working Group
Date:  November 11, 2015
Time: 9:00 a.m. – 12:00 p.m.
Location: Exar, Fremont, CA

Presentations

What's New in this Group?
NOV 13, 2014
AUG 21, 2014
FEB 23, 2014
NOV 13, 2013
AUG 22, 2013
MAY 13, 2013
FEB 13, 2013

Minutes

What's New in this Group?

2014 Meeting Minutes

2013 Meeting Minutes

News

What's New in this Group?

Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.

Litho Options Sparse After 10nm
Thursday, October 16, 2014
Semiconductor Engineering
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

200mm fabs: Older but thriving
Wednesday, October 15, 2014
EETimes Asia
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.

Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
3D InCites
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.

MEMS treads logic road
Wednesday, August 6, 2014
EETimes Asia
Across the industry, it is becoming more and more evident that the MEMS sector will follow a similar path to CMOS logic. That path is one in which integrated device manufacturers (IDMs) that do everything thing under one roof will progressively give way to those choosing one side or other of a dual fabless-foundry business model, where there are those that specialise in manufacturing in volume and those that specialise in design.

TSMC Details Family of Chip Stacks
Thursday, April 24, 2014
EE Times
TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations. The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.

3D EDA brings together proven 2D solutions
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year. "This is unprecedented," said Kelvin Low, senior director of marketing at Samsung. "It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model," he added. Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

Fast & Accurate Thermal Analysis of 3D-ICs
Monday, April 14, 2014
SemiWiki
As Moore's law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it's extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, Tmax control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.

FinFET Custom Design
Wednesday, April 2, 2014
SemiWiki
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel
Wednesday, March 19, 2014
3D InCites
All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it's clear that we've got some very different opinions regarding one of my pet peeves - the ever-expanding and increasingly complex advanced packaging nomenclature.

Silicon Photonics Bring New Capabilities To IC Design
Tuesday, March 18, 2014

These days, electronic systems and products are always looking for increased communication speed and lower power consumption. Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth. Early applications to short-run data communications in the data center, described by Intel and Cisco among others, are capturing attention in the press. With the world headed toward the Internet of Everything, more capable and efficient server farms are interesting to many.

Plug-and-play test strategy for 3D ICs
Monday, March 17, 2014
Solid State Technology
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield. Yield is typically determined using silicon area as a key factor; the larger the die, the more likely it contains a fabrication defect. One way to improve yield, then, is to segment the large and potentially low-yielding die into multiple smaller die that are individually tested before being placed together in a 3D IC.

Big sell: IP trends and strategies
Tuesday, March 11, 2014
Semiconductor Manufacturing & Design
Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

Exploring circuit design in FinFET technology
Monday, March 10, 2014
EE Times Asia
The major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for their 14 nm processes. As with any new process technology, the most important question to an IC designer is "What does this mean to me?"

A Flexible Test Strategy for 3D ICs
Thursday, March 6, 2014
EEJournal
The semiconductor industry is ramping up for the wider adoption of 3D ICs, which promise better performance, reduced power, and improved yield. While some aspects of true 3D ICs are still evolving, solutions for testing 3D ICs are ready today. The test strategy for 3D ICs has two goals: improving the pre-packaged test quality and establishing new tests between the stacked dice. We describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die, stack, and partial stack-level tests to use the same test interface, and to retarget die-level tests directly to the selected die within the 3D stack.

JUST IN: Comcast buys Time Warner Cable for $45.2 billion: Is deal pro consumer, business? Topic: Apple Discover Follow via: RSSEmail Alert Greenpeace praises Apple for cutting conflict minerals, supply chain transparency
Thursday, February 13, 2014
ZDNet
Apple's increased transparency about its suppliers is becoming a hallmark of Tim Cook's leadership at the company. Apple has flexed its muscles in the past to push suppliers to remove hazardous substances from products and provide more renewable energy for data centers, and it is proving the same model can work to reduce the use of conflict minerals. Samsung and other consumer electronics companies should follow Apple's example and map its suppliers, so the industry can exert its collective influence to build devices that are better for people and the planet.

Cost-efficient 3D IC wafer processing without adhesives
Monday, January 27, 2014
EE Times Asia
During a 3D TSV Summit on Minatech' campus in Grenoble, France, a resounding topic across the floor was on how to cut costs in 3D IC packaging. Disregarding IC design, there are many processes involved before dies can be stacked together. These include the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.

Glass Interposers
Monday, January 6, 2014
Electronic Engineering Journal
There's been lots of discussion of the silicon interposer as a way to ease us into the world of 3D-packaged ICs. The silicon interposer is the main enabler for what's typically referred to as 2.5D packaging; it acts like a high-quality micro-PCB that can be built using the silicon manufacturing infrastructure that's already in place.

HOME

Tools

What's New in this Group?

Introduction to the Supply Chain Merger & Acquisition and Integration Due Diligence

The Global Semiconductor Alliance (GSA) formed a Supply Chain Technology Team several years ago. This team meets quarterly to review Supply Chain Best Practices and develop tools that enhance the flow of material and information throughout the supply chain.

Objective of this document

Define a broad spectrum of items that must be considered by Supply Chain management of both companies in a merger or acquisition.  This initial release is targeted toward the Supply Chain Professional and is not yet all encompassing.  Future work will extend the checklist to include Legal, Financial, Human Resources, and IT aspects.

Checklist Usage

  • This Checklist assumes that first order Due Diligence has been completed and companies are moving toward integration.
  • This checklist does not try to capture all aspects of M&A / Integration requirements.
  • This checklist does try to provide food for thought in the areas of Manufacturing, Operations, and Supply Chain.
  • Purpose of this checklist is to facilitate integration
  • In numerous areas, answering yes a particular line item will lead to a much deeper investigation.
  • We have not attempted to answer or provide Financial or Legal advice or interpretation.
  • Moving forward with an M&A / Integration, this Checklist should be tailored to reflect your situation.
  • Treat as M&A Audit Tool
  • Confirm Checklist & Procedures meet your requirements and situation
  • Generate Test Cases to Confirm
  • This checklist is openly available to anyone in the industry.
  • Feedback should be sent to hbeasley@gsaglobal.org

Notes

  • Treat as M&A Audit Tool
  • Confirm Checklist & Procedures meet your requirements and situation
  • Generate Test Cases to Confirm
  • This checklist is openly available to anyone in the industry.
  • Feedback should be sent to hbeasley@gsaglobal.org

Initial Release Date: October 15, 2014

Conflict Minerals

What are Conflict Minerals?

Congress passed the Dodd-Frank Act in 2010, with S1502 addressing the use of Conflict Minerals (Tantalum, Tin, Tungsten, Gold) that are mined in the Democratic Republic of Congo (DRC) and surrounding countries.

This Act applies to any company that files periodic reports under Sections 13(a) or 15(d) of the Exchange Act who:

  • Manufactures or contracts to manufacture products, and
  • Conflict minerals are necessary to the functionality or production of those products

Each company must determine at a product level how S1502 applies.  The company is then required to develop and conduct reasonable country of origin inquiry (RCOI) and due diligence (DD).  The results must be disclosed with annuals filings.  The purpose of this reporting requirement is to reduce funding for armed groups in the DRC and surrounding countries.

GSA is gathering information for our membership to help ensure everyone is fully informed of these requirements.  Below is a recent presentation from PwC, as well as links to other pertinent material.

Questions may be directed to the Director, Technology:

Harrison Beasley
hbeasley@gsaglobal.org
C 972.489.0248

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