Supply Chain Working Group

  • Overview
  • Meeting Schedule
  • Presentations
  • Minutes
  • News
  • Projects
  • Conflict Minerals

Overview

What's New in this Group?

An efficient and effective semiconductor supply chain addresses every aspect of wafer fabrication, die assembly and test, and product delivery.  The supply chain performs Capacity versus Demand analysis; Capacity Trending, and other issues that could impact successful flow of product.  With the rapid rise of decreased cycle times due to quickly changing consumer markets, the supply chain is under new stresses to ensure a steady supply flow.

Vision

Analyze wafer and assembly pricing trends.   Address supply chain impacts and risks due rapidly changing development needs.  Provide an efficient response capability to statutory regulations.

Mission

Provide an open forum where supply chain executives openly discuss risks and impact due to semiconductor industry consolidation, single point failures, advanced packaging initiatives, and other areas of supply chain management.

Objectives
  • Quarterly wafer and assembly pricing trend analysis
  • Generate reports to address the changing landscape of semiconductor supply chain management
  • Risk assessment and mitigation techniques
  • Best practices sharing
  • Provides information and guidance for Conflict Minerals and other statutory regulations
Initiatives

Wafer Fabrication & Assembly Pricing Survey/Report – The Wafer Fabrication & Assembly Pricing Survey queries fabless companies and IDMs on pricing trends for outsourced wafers and assembly services.  The report includes a written analysis of results and  an interactive online database that allows tailored analysis of wafer pricing, mask set pricing, and assembly pricing.

Contact Information

Harrison Beasley
972.489.0248
hbeasley@gsaglobal.org

Working Group Chair
Dan Wark, Vice President, Supply Chain Management, Exar Corporation

Meeting Schedule

What's New in this Group?
Q2 2014 Meeting

Supply Chain Working Group
Date: May 8, 2014
Time: 9:00 a.m. – 12:00 p.m.
Location: Exar, Fremont

Q3 2014 Meeting

Supply Chain Working Group
Date: August 21, 2014
Time: 9:00 a.m. – 12:00 p.m.
Location: Silicon Valley

Q4 2014 Meeting

Supply Chain Working Group
Date:  November 13, 2014
Time: 9:00 a.m. – 12:00 p.m.
Location: TBD

Q1 2015 Meeting

Supply Chain Working Group
Date: February 19, 2015
Time: 9:00 a.m. – 12:00 p.m.
Location:

Presentations

What's New in this Group?

Feb 23, 2014

Nov 13, 2013

Aug 22, 2013

May 13, 2013

Feb 13, 2013

Minutes

What's New in this Group?

2013 Meeting Minutes

News

What's New in this Group?

3D EDA brings together proven 2D solutions
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Thursday, April 17, 2014
Semiconductor Manufacturing & Design
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year. "This is unprecedented," said Kelvin Low, senior director of marketing at Samsung. "It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model," he added. Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

Fast & Accurate Thermal Analysis of 3D-ICs
Monday, April 14, 2014
SemiWiki
As Moore's law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it's extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, Tmax control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.

FinFET Custom Design
Wednesday, April 2, 2014
SemiWiki
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor, it gets harder with each process generation. I'm going to leave verification until another blog.

Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel
Wednesday, March 19, 2014
3D InCites
All hell broke loose at the 3D Panel discussion at the 2014 IMAPS International Device Packaging Conference. Nobody was hurt, and nothing got thrown, mind you, but it's clear that we've got some very different opinions regarding one of my pet peeves - the ever-expanding and increasingly complex advanced packaging nomenclature.

Silicon Photonics Bring New Capabilities To IC Design
Tuesday, March 18, 2014

These days, electronic systems and products are always looking for increased communication speed and lower power consumption. Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth. Early applications to short-run data communications in the data center, described by Intel and Cisco among others, are capturing attention in the press. With the world headed toward the Internet of Everything, more capable and efficient server farms are interesting to many.

Plug-and-play test strategy for 3D ICs
Monday, March 17, 2014
Solid State Technology
Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield. Yield is typically determined using silicon area as a key factor; the larger the die, the more likely it contains a fabrication defect. One way to improve yield, then, is to segment the large and potentially low-yielding die into multiple smaller die that are individually tested before being placed together in a 3D IC.

Big sell: IP trends and strategies
Tuesday, March 11, 2014
Semiconductor Manufacturing & Design
Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

Exploring circuit design in FinFET technology
Monday, March 10, 2014
EE Times Asia
The major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for their 14 nm processes. As with any new process technology, the most important question to an IC designer is "What does this mean to me?"

A Flexible Test Strategy for 3D ICs
Thursday, March 6, 2014
EEJournal
The semiconductor industry is ramping up for the wider adoption of 3D ICs, which promise better performance, reduced power, and improved yield. While some aspects of true 3D ICs are still evolving, solutions for testing 3D ICs are ready today. The test strategy for 3D ICs has two goals: improving the pre-packaged test quality and establishing new tests between the stacked dice. We describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die, stack, and partial stack-level tests to use the same test interface, and to retarget die-level tests directly to the selected die within the 3D stack.

JUST IN: Comcast buys Time Warner Cable for $45.2 billion: Is deal pro consumer, business? Topic: Apple Discover Follow via: RSSEmail Alert Greenpeace praises Apple for cutting conflict minerals, supply chain transparency
Thursday, February 13, 2014
ZDNet
Apple's increased transparency about its suppliers is becoming a hallmark of Tim Cook's leadership at the company. Apple has flexed its muscles in the past to push suppliers to remove hazardous substances from products and provide more renewable energy for data centers, and it is proving the same model can work to reduce the use of conflict minerals. Samsung and other consumer electronics companies should follow Apple's example and map its suppliers, so the industry can exert its collective influence to build devices that are better for people and the planet.

Cost-efficient 3D IC wafer processing without adhesives
Monday, January 27, 2014
EE Times Asia
During a 3D TSV Summit on Minatech' campus in Grenoble, France, a resounding topic across the floor was on how to cut costs in 3D IC packaging. Disregarding IC design, there are many processes involved before dies can be stacked together. These include the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.

Glass Interposers
Monday, January 6, 2014
Electronic Engineering Journal
There's been lots of discussion of the silicon interposer as a way to ease us into the world of 3D-packaged ICs. The silicon interposer is the main enabler for what's typically referred to as 2.5D packaging; it acts like a high-quality micro-PCB that can be built using the silicon manufacturing infrastructure that's already in place.

China's SMIC Responds to Soaring 3D IC Market
Monday, October 21, 2013
EE Times
In hopes of getting a piece of action in the rapidly growing thru-silicon-via technology-based 2.5D and 3D IC market, China's leading foundry, Semiconductor Manufacturing International Corp. (SMIC), announced Monday that it has formed an R&D and manufacturing center dedicated to vision, sensors, and 3D IC.

Xilinx, TSMC reach volume production on 28nm 3D ICs
Monday, October 21, 2013
DigiTimes
Xilinx and TSMC have jointly announced production release of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous 3D ICs in production. With this milestone, all Xilinx 28nm 3D IC families are now in volume production. These 28nm devices were developed on TSMC's chip-on-wafer-on-substrate (CoWoS) 3D IC process that produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device, the companies said.

TU Delft, Imec co-author test flow for 3D IC optimisation
Friday, October 11, 2013
EE Times Asia
The Delft University of Technology and Imec recently co-developed a new test flow cost modelling tool for 2.5 and 3D stacked integrated circuits. 3D-COSTAR aims to optimise the test flow of 3D stacked ICs by compiling the yields and costs of design, manufacturing packaging and logistics.

Analog Drives Processor Architecture
Thursday, October 3, 2013

The recent port of a number of mixed signal interface IP blocks to 20nm by Synopsys Inc raises some fascinating questions on the microprocessor ecosystem. In days gone by, analog was well behind the curve. Now, USB, DDR, PCI Express, and MIPI PHY interfaces are available at what is pretty much the leading edge.

MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards
Wednesday, August 14, 2013
Cadence Blog
Much has been said about a "memory wall" that emerges when the throughput needs of the system outstrip the performance of the memory. One possible solution is to leap right over that wall with high-bandwidth 3D-IC solutions. But there's both promise and peril with emerging 3D-IC memory standards, according to panelists at the MemCon conference August 6, 2013.

Addressing the IP security challenge
Tuesday, August 6, 2013
EE Times India
A company's success, as well as its future, depends on the creation and successful defence of intellectual property (IP), which is generally defined as "creations of the mind for which exclusive rights are recognised." IP is the outcome of innovation and work done by an organisation/person and gives a company's products an edge over competitors.

Ultra-low power IP sub-system for sensors
Thursday, August 1, 2013
EE Times India
Synopsys Inc. has debuted its DesignWare Sensor IP Sub-system that the company describes as a complete and integrated hardware and software solution for sensor control applications. The IP sub-system is optimised to process data from digital and analogue sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power, detailed the firm.

Hybrid Memory Cube nears engineering sample milestone
Wednesday, July 17, 2013
Solid State Technology
Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

Silicon Photonics: the Next Killer App for 3D ICs? and more from the R&D Community
Tuesday, July 16, 2013
3D InCites
First it was going to be memory stacks, then it was Wide I/O DRAM on Memory, and now, as commercialization of 3D ICs gets pushed out further, will it be Silicon Photonics that drives 3D ICs to volume manufacturing? That was the opinion expressed by Michael Liehr, executive VP of Executive VP CNSE, during the SEMICON West 2013 R&D Panel - "A Conversation on the Future of Semiconductor Technology", which I attended on July 10, 2013.

Testing an IC Sandwich
Friday, July 12, 2013
SemiWiki
At a lovely, but chilly, 3DIncites awards breakfast during SEMICON West, I saw Mentor Graphics win in two of five categories (Calibre 3DSTACK was the other winner). Afterwards, I talked to Steve Pateras, the product marketing director of Mentor's test solutions about Tessent Memory BIST, which was one of the winners. I asked Pateras to explain why his memory BIST (built-in self test) tool stood out.

Materials Improvements Boosting IC Performance
Thursday, July 11, 2013
EE Times
Improvements in semiconductor materials are now responsible for about 90 percent of the performance improvement of ICs at each node, significantly more than the roughly 15 percent they contributed in 2000, according to Schubert Chu, head of Applied Materials Inc.'s epitaxy unit.

Dow Corning joins imec for advancement of enabling technologies for 3D-IC
Tuesday, July 9, 2013
Solid State Technology
Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics. The announcement signals expanded opportunities for both organizations to combine their expertise toward the development and broader adoption of 3D integrated circuit (IC) packaging technologies, wherein IC chips are stacked in vertical 3D architectures.

HOME | OLDER HEADLINES

Projects

What's New in this Group?

Merger & Acquisitions Due Diligence

The Supply Chain Working Group began defining M&A Due Diligence Checklists in 3Q13.  Through biweekly calls, the below document will be refined and offered to the GSA membership for consideration.

Merger & Acquisition Due Diligence (Google Docs)

 

 

Conflict Minerals

What's New in this Group?

Semiconductor Conflict Minerals Compliance Workshop 03.19.14

Conflict Mineral Compliance reporting is a new requirement for public companies that file with the SEC. It impacts not only public companies, but private companies that sell directly or indirectly to public companies.  This workshop will cover and clarify those requirements; additional details available here.

What are Conflict Minerals?

Congress passed the Dodd-Frank Act in 2010, with S1502 addressing the use of Conflict Minerals (Tantalum, Tin, Tungsten, Gold) that are mined in the Democratic Republic of Congo (DRC) and surrounding countries.

This Act applies to any company that files periodic reports under Sections 13(a) or 15(d) of the Exchange Act who:

  • Manufactures or contracts to manufacture products, and
  • Conflict minerals are necessary to the functionality or production of those products

Each company must determine at a product level how S1502 applies.  The company is then required to develop and conduct reasonable country of origin inquiry (RCOI) and due diligence (DD).  The results must be disclosed with annuals filings.  The purpose of this reporting requirement is to reduce funding for armed groups in the DRC and surrounding countries.

GSA is gathering information for our membership to help ensure everyone is fully informed of these requirements.  Below is a recent presentation from PwC, as well as links to other pertinent material.

Questions may be directed to the Working Groups Manager:

Harrison Beasley
hbeasley@gsaglobal.org
C 972.489.0248

Bookmark the permalink.
UMCCalibreAmkor TechnologyRevitasTSMCSamsungeSilicon