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The GSA EMTECH Interest Group has invited Trent Uehling, Technical Director in the Package Innovation Group under the CTO office of NXP Semiconductor for the February 2024 webinar. Trent will present on the topic of “Chiplets and Advanced Packaging” and discuss how advanced packaging technologies are enabling the chiplet revolution. He will also cover developments in the Chiplet Interface Standards and Chiplet Advanced Packaging Marketplace.

Chiplets & Advanced Packaging

Date/Time: Thursday, February 29, 2024 | 8:00 – 9:00 AM PST


Trent Uehling
Technical Director, Package Innovation, CTO Office
NXP Semiconductor

The So-Called “Chiplet Revolution”.

As the chiplet concept is making its way into products, some are declaring a “chiplet revolution” in the semiconductor industry.  The term revolution is used because of the paradigm shift from large, monolithic SOCs to thoughtful disaggregation of chips into functional parts, or “chiplets”.  Multi-chip packaging has been in use for decades.  So, why so much recent attention on this chiplet concept?   This time, the movement is spurred largely by the slowing of Moore’s law and the need to accelerate performance by methods other than semiconductor node progression.  Modern advanced packaging technologies are enabling multi-chip packaging with minimal or no impact on device performance and power consumption at a competitive cost.  IDMs, OSATs, and wafer foundries are determining their roles in the design and packaging of chiplet systems.

Chiplet Interface Standards – Business Driver or Commodity?

Standardized interfaces enable the integration of multiple suppliers and also enable start-ups to gain traction in IDM designs.  Efforts are underway to develop standards that are optimized for bandwidth, latency, and power.  However, the standardization and interoperability requirements will likely add some overhead in these areas.  An interesting development related to chiplet interface standards may be the emergence of an “Integrator” function for the design and packaging of chiplet systems, similar to the “System on Module” (SOM) providers today.  It is speculated by some that this concept may lead to some semiconductor IP being “commodified” similar to what happened to some memory technologies in the past.  Industry-wide standards can also create synergy for evolving and improving the interfaces, contributing to the overall value of advanced packaging.

Chiplet Advanced Packaging Marketplace

The advanced packaging market is expected to grow at a significant pace, largely driven by chiplets.  Historically considered a “necessity” to connect chip power and signals, packaging now brings more value to the system solution.  As I/O density and bandwidth increase, so does package cost. The key is to “right-size” technology to meet bandwidth and cost targets.  Each part of the semiconductor manufacturing value chain will have its place in chiplet packaging.  OSATs and IDMs will likely drive advanced packaging for low to mid-performance devices utilizing 2D on substrate, fan-out, bridge, and passive interposer technologies.  Wafer foundries and limited IDMs will play more in the high-performance arena with technologies such as 3D die stacking and hybrid bonding.  Suppliers of BOM components such as silicon and glass interposers will also benefit from the increased application of advanced packaging.

What’s Next?

Chiplet packaging is the next generation in advanced packaging to achieve performance and power comparable to SOC.  Chiplet standard and proprietary interfaces will continue to evolve, driving IP and packaging technologies.  The added value contribution for advanced packaging will act as a catalyst for the growth of advanced packaging, enabling improved time to market, portfolio expansion and R&D efficiency to chip IDMs.  Government funding initiatives such as the US CHIPs Act are accelerating advance packaging development.


Trent Uehling
Technical Director / Package Innovation, CTO Office
NXP Semiconductor

Trent Uehling is a Technical Director in the Package Innovation Group under the CTO office of NXP Semiconductor.  He is the lead for Chiplet Advanced Packaging at NXP and has broad experience and deep expertise in advanced semiconductor packaging technologies, chip-package interactions, and system codesign and applications.

He has partnered with customers, suppliers, consortiums, universities, and government entities to develop advanced packaging strategies and technologies, and is active in industry standards definitions for chiplets.

Trent holds a Bachelor of Science degree in Mechanical Engineering from Michigan Technological University.

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