PDKs Can Enable an Open Market for Interposer and 3D Solutions
Tuesday, November 25, 2014
As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM).
Texas Instruments announces 22B copper wire bond technology units shipped
Friday, October 17, 2014
Solid State Technology
Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial. The majority of TI's existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond. Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold. It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI's analog and embedded processing parts.
Litho Options Sparse After 10nm
Thursday, October 16, 2014
With EUV's viability still uncertain, multi-patterning may be the cheapest option at 7nm. Beyond that, 3D architectures could be a game changer. Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in Lithography [KC], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.
200mm fabs: Older but thriving
Wednesday, October 15, 2014
With shrinking device geometries, semiconductor companies are upgrading to larger wafer sizes to reap cost benefits resulting from larger number of dice per wafer. Worldwide, many fabs moved to 300mm wafers more than a decade ago, and Europeans are now talking about the 450mm transition as "opportunities for Europe." The case notwithstanding, there is still plenty of life remaining in 200mm fabs, according to IC Insights, noting that not all semiconductor devices can take advantage of the cost savings 300mm wafers can provide.
Designing in 3D? Don't Make These DFT Mistakes
Wednesday, October 8, 2014
The semiconductor industry hasn't adopted 3D ICs as quickly as many in the industry expected. There are some barriers that perhaps have kept the cost/benefit analysis stuck in the 'scaling' camp rather than moving it to the '3D' camp. However, many companies are preparing for the move to 2.5D and 3D in the future. From a DFT perspective, the barriers are actually quite low; designers have methodologies now to stack their memory on logic, including the ability to test stacked ICs. The test strategy for 3D ICs has two goals: to support high yields and to establish plug-and-play DFT and test patterns. From our DFT perspective, there are a few mistakes you can avoid when thinking about designing, or beginning the design, of 3D ICs.